Dynamic random access memory array having a cross-point layout,

Details Dynamic random access memory array having a cross-point layout, Dynamic random access memory array having a cross-point layout,

1995-01-26

1996-03-05

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257302, 257330, 257382, H01L 27108, H01L 2976

Patent

active

054970172

ABSTRACT:
This invention is a DRAM array having stacked-capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a 5-mask process for fabricating such an array. The array has a cross-point cell layout (i.e., a memory cell is located at each intersection of each digit line and each word line) and tungsten digit lines formed using a damascene process buried in the substrate. Each cell in the array has a vertical transistor, with the source/drain regions and channel region of the transistor being formed from epitaxially grown single crystal silicon. The stacked capacitor is fabricated on top of the vertical transistor.

REFERENCES:
patent: 4974060 (1990-11-01), Ogasawara
patent: 5276343 (1994-01-01), Kumagai et al.
patent: 5281837 (1994-01-01), Kohyama
patent: 5410169 (1995-04-01), Yamamoto et al.

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