Dynamic random access memory and manufacturing method thereof

Details Dynamic random access memory and manufacturing method thereof Dynamic random access memory and manufacturing method thereof

1995-08-07

1997-02-04

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365179, 36518901, G11C 1300

Patent

active

056005911

ABSTRACT:
A memory cell structure with the reduced number of bit line contacts, contributing to high integration and high reliability of a DRAM is provided. Each of memory cells (M1, M2, M3, M4) of the DRAM includes a field effect transistor and a capacitor (I, II, III, IV) connected thereto. The field effect transistor constituting each of the memory cells has a combination of two gates: a transfer gate (A) of a low Vth and a sub-transfer gate (a) of a high Vth, a transfer gate (B) of a high Vth and a sub-transfer gate (b) of a low Vth, a transfer gate (C) of a high Vth and a sub-transfer gate (c) of a low Vth, and a transfer gate (D) of a low Vth and a sub-transfer gate (d) of a high Vth. The four memory cells share a bit line contact.

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patent: 3706079 (1972-12-01), Vadasz
patent: 3868654 (1975-02-01), Itoh
patent: 4021788 (1977-05-01), Marr
patent: 4503519 (1985-03-01), Arakawa
patent: 5181188 (1993-01-01), Yamaguchi et al.
patent: 5293563 (1994-03-01), Ohta

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