Dynamic random access memory and fabrication thereof

Details Dynamic random access memory and fabrication thereof Dynamic random access memory and fabrication thereof

2006-10-10

2006-10-10

Dang, Phuc T. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S066000, C257S305000

Reexamination Certificate

active

07119390

ABSTRACT:
A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

REFERENCES:
patent: 6608341 (2003-08-01), Schrems

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