Dynamic random access memory and a method of operating the same

Details Dynamic random access memory and a method of operating the same Dynamic random access memory and a method of operating the same

1991-02-20

1992-04-07

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518901, G11C 1300

Patent

active

051034239

ABSTRACT:
A dynamic RAM includes a memory cell comprised of a data read transistor, a data write transistor and a data storage capacitor. The data write transistor is turned on in response to a row selection signal to connect the capacitor to a write bit line. The dynamic RAM includes a structure for shifting the level of potential of internal write data to be transmitted onto the write bit line. This structure will prevent the data write transistor from being turned on by the undershoot produced on the write bit line.

REFERENCES:
patent: 5036491 (1991-07-01), Yamaguchi et al.
"Introduction to MOS LSI Design", by J. Maber, Translated by T. Sugano et al., Apr. 20, 1984.

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