Static information storage and retrieval – Read/write circuit – Differential sensing
Patent
1982-09-30
1985-05-28
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Differential sensing
G11C 700, G11C 1140
Patent
active
045204667
ABSTRACT:
A dynamic random access memory comprises a one-transistor type MOS dynamic random access memory of an open bit line type, which comprises two memory arrays at the left and the right sides of sense amplifying circuits (2). Each of both memory arrays comprises a plurality of memory cells (1) and dummy cells (3), each of columns of memory cells (1) and dummy cells (3) having a cell plate voltage control circuit (13) connected at the end thereof through a cell plate (8). Each cell plate voltage control circuit (13) is provided with a control signal .phi..sub.G having a level changing during a period when any of word lines (5) or dummy word lines (6) is selected and is responsive to selection of the word line (5) or the dummy word line (6) to discharge the voltage of the cell plate (8) and is responsive to a change of the level of the control signal .phi..sub.G to charge the cell plate (8). Accordingly, transfer of a signal electric charge from the memory cell (1) and the dummy cell (3) to the bit line (4) is performed at a high speed, and delay of the signal of the word line (5) and the dummy word line (6) is compensated, whereby a high speed operation can be performed. In addition, a signal electric charge stored in the memory cells (1) and the dummy cells (3) is increased and the operation is accordingly stabilized.
REFERENCES:
patent: 3959781 (1976-05-01), Mehta et al.
patent: 4136401 (1979-01-01), von Basse
patent: 4195357 (1980-03-01), Kuo et al.
patent: 4393474 (1983-07-01), McElroy
Stein, Karl U. et al., "Storage Array and Sense/Refresh Circuit for Single-Transistor Memory Cells", IEEE Journal of Solid-State Circuits, vol. SC-7, No. 5, Oct. 1972.
Mitsubishi Denki & Kabushiki Kaisha
Moffitt James W.
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