Dynamic random access memory

Details Dynamic random access memory Dynamic random access memory

1994-01-28

1995-01-17

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Serial read/write

365210, 36523001, G11C 1300

Patent

active

053831608

ABSTRACT:
A DRAM includes a memory cell array having cascade-connected type memory cells arranged in a matrix form and each capable of storing plural-bit information in the unit of bit, sense amplifiers each arranged for a preset number of columns in the memory cell array and disposed in the central portion of the bit lines of the preset number of columns in the arrangement direction, switching circuits disposed on both sides of each of the sense amplifiers, for electrically and selectively connecting the preset number of columns to the sense amplifier, an address designation circuit for separately and serially designating addresses of a plurality of memory cells disposed on both sides of the sense amplifier in the same column of the memory cell array, a word line driving circuit for selectively driving a word line connected to a memory cell of an address designated by the address designation circuit, a column selection circuit for effecting the column selection of the memory cell array, and an access control circuit for time-serially reading out plural-bit information from one of the memory cells storing storage information and lying on one side of the sense amplifier and sequentially rewriting the plural-bit information into one of the memory cells lying on the other side of the sense amplifier and set in a non-use state at the time of serial access to a plurality of memory cells in a desired column of the memory cell array.

REFERENCES:
patent: 5317540 (1994-05-01), Furuyama
Kimura et al., "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture" ISSC91, Feb. 1991.

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