Dynamic random access memory

Details Dynamic random access memory Dynamic random access memory

2001-01-05

2002-01-29

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S196000

Reexamination Certificate

active

06343043

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic random access memory (hereafter referred to as “DRAM”) which must be refreshed in order to hold data.
2. Description of the Related Art
A DRAM with a large memory capacity is normally provided with a memory cell array constituted of a plurality of memory blocks for data storage. As various mobile products with battery-driven systems have become distributed in ever-increasing numbers in the market in recent years, it has become necessary for DRAM installed in such systems to operate at a lower voltage level and achieve lower power consumption.
The structure of memory cells in DRAM require a refresh operation be performed in order to hold data stored in memory. The refresh operation must be performed continually as long as the stored data are to be sustained, regardless of whether they apparatus or the system in which the DRAM is installed is in an active state or a suspended state.
FIG. 2
is a block diagram of a self refresh control circuit in a DRAM in the prior art.
DRAM in the prior art is provided with a self refresh control circuit, as illustrated in
FIG. 2
to achieve self refresh.
Self refresh in the DRAM refers to a refresh operation performed by using a row address strobe signal RASB (the “B” at the end of the code indicates the anti-phase) that, when set to “L”, indicates an active state, and a column address strobe signal CASB that, when set to “L”, indicates an active state. The refresh is performed when the signal CASB set to “L” after the setup time elapses has been held at “L” over a specific length of time or longer before the signal RASB is set to “L”.
The self refresh control circuit is provided with a refresh decision-making circuit
3
connected to an RASB pad
1
, through which the signal RASB is input, and a CASB pad
2
, through which the signal CASB is input. The refresh decision-making circuit
3
makes a decision as to whether or not a self refresh is requested based upon the signal RASB and the signal CASB, and accordingly generates a refresh enable signal SREF. The output side of the refresh decision-making circuit
3
is connected to a refresh timer
4
, a refresh control circuit
5
, a refresh counter
6
and an X address buffer
7
.
The refresh timer
4
, which is activated by the signal SREF, has a function of providing a refresh request signal RREQ to be used as a timing signal to the refresh control circuit
5
. The refresh counter
6
, which is activated by the signal SREF, generates a refresh address RA (
0
:i) with an (i+1) bit width for a refresh based upon a counter control clock RCLK. The refresh control circuit
5
, which is activated by the signal SREF, outputs an RAS signal for internal use (hereafter referred to as an internal RAS) based upon the signal RREQ, with its output side connected to one of the input terminals of a two-input NOR gate
8
via a node N
1
. The other input terminal of the NOR gate
8
is connected to the signal RASB pad
1
, and the output terminal of the NOR gate
8
is connected to an RAS system circuit
11
via two-stage inverters
9
and
10
.
The RAS system circuit
11
, which is constituted of a sense amplifier that amplifies the potential difference between individual bit lines BL and BLB in a bit line pair, a timing generator that generates a timing signal (neither shown) and the like, provides the counter control clock RCLK to the refresh counter
6
and provides an X address latch signal LH to the X address buffer
7
.
An X address AX (
0
:i) for normal access is input to the X address buffer
7
through an address pad
12
. When the signal SREF is set to “H”, the refresh address RA (
0
:i) is stored, whereas the X address AX (
0
:i) is stored if the signal SREF is at “L”. An X pre-decoder
13
and a plurality of X decoders
14
-
1
,
14
-
2
, . . . are connected to the output side of the X address buffer
7
. The X pre-decoder
13
decodes the address stored at the X address buffer
7
to select a memory block, and outputs the X address corresponding to the selected memory block as a pre-decode signal, which is then provided to the X decoders
14
-
1
,
14
-
2
, . . . One of the X decoders
14
-
1
,
14
-
2
. . . is selected by the pre-decode signal, and the pre-decode signal is then decoded by the selected X decoder to select a word line WL of the memory block connected to the X decoder.
FIG. 3
is a waveform diagram corresponding to the operation explained in reference to FIG.
2
. In reference to
FIG. 3
, the self refresh operation is summarized.
Based upon the signal RASB and the signal CASB, the refresh decision-making circuit
3
generates a refresh enable signal SREF at “H”. When the signal SREF is at “H”, the refresh timer
4
automatically sets the refresh request signal RREQ to “H” intermittently. Thus, the internal RAS provided to the RAS system circuit
11
alternates between H and L repeatedly. The RAS system circuit
11
provides the counter control clock RCLK to the refresh counter
6
, and the refresh counter
6
sequentially outputs the refresh addresses RA (
0
:i) in synchronization with the counter control clock RCLK. As a result, the refresh addresses RA (
0
:i) are stored at the X address buffer
7
, and the refresh addresses RA (
0
:i) are decoded by the X pre-decoder
13
and the X decoders
14
-
1
,
14
-
2
. . . In addition, the word line WL at the selected memory block is selected and the memory cells (not shown) connected to the word line WL become refreshed. This self refresh operation is repeated as long as the signals RASB and CASB remain at “L”.
However, the following problem is yet to be addressed with regard to the DRAM in the prior art.
FIG. 4
illustrates the problem of the DRAM in the prior art.
A plurality of memory cells in the DRAM are constituted as, for instance, two 256 kilo-bit (256 kb) memory cell array blocks ABLK
1
and ABLK
2
. Word lines WL inside the individual blocks ABLK
1
and ABLK
2
are respectively selected by the X decoders
14
-
1
and
14
-
2
, and bit line pairs BL and BLB inside the two blocks ABLK
1
and ABLK
2
are selected by a common Y decoder
15
. It is assumed that either one of the blocks ABLK
1
or ABLK
2
is selected in correspondence to the levels of the highest-order bit signal A
8
X and the X address AX (
0
:i) and a signal A
8
XB at the anti-phase of the signal A
8
X. The signals A
8
X and A
8
XB are pre-decoded by the X predecoder
13
, and either one of the two blocks ABLK
1
and ABLK
2
is selected. The one block ABLK
1
or ABLK
2
selected by the signals A
8
X and A
8
XB in this process is a block that is not required to hold data. Since both blocks ABLK
1
and ABLK
2
undergo the self refresh process regardless of whether or not they need to hold data, power is consumed in a wasteful manner, and thus, it does not satisfy the technological requirement of lower power consumption.
For instance, when the DRAM is utilized to store messages in a mobile telephone or the like, while it is necessary to perform a self refresh for the block (e.g., the block ABLK
1
) having messages stored therein, the other block ABLK
2
does not need to be refreshed. However, since a self refresh is performed for the block ABLK
2
which does not need to be rereshed as well in the DRAM in the prior art, battery power is unnecessarily depleted.
SUMMARY OF THE INVENTION
In order to address the problem of the prior art discussed above, in a first aspect of the present invention, a DRAM comprising a plurality of blocks each provided with a plurality of word lines selected by an X address, a plurality of bit lines and a plurality of memory cells for data storage connected to the word lines and the bit lines, a refresh decision-making circuit that detects whether or not a refresh is requested for the plurality of memory cells based upon a control signal provided from the outside and makes a decision with regard to its mode, a refresh timer that is activated when the result of the decision-making performed by the refresh decision-making circuit indica

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