Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-29
2001-07-03
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S242000
Reexamination Certificate
active
06255683
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a dynamic random access memory (DRAM), and more particularly, to a DRAM that comprises a semiconductor chip (body) in which an array of memory cells are arranged in rows and columns, each memory cell including a switch in series with a storage capacitor in which bits are written in and read out under control of the switch.
BACKGROUND OF THE INVENTION
DRAMs of the kind that use a switch in series with a capacitor for storage are among the most important of all integrated circuits. A continuing trend in DRAMs is the increase in the number of memory cells that are stored in a single chip, a number that is now in the millions and is still increasing.
It is desirable to decrease the size of individual memory cells of the array so as to increase the capacity of DRAMs while limiting the size of the semiconductor chip. A popular memory cell uses an n-channel metal oxide semiconductor transistor (MOSFET), also known as an insulated gate field effect transistor (IGFET), as the switch and a capacitor. The use of a storage capacitor that is formed as a deep vertical trench in the chip, adjacent the transistor with which it is in series, is widespread. Associated with such a trend is a trend towards the use of a vertical transistor formed at the top of the trench to increase still further the number of cells that can be formed in a single semiconductor chip.
A problem that has arisen in a memory cell that uses both a vertical trench storage capacitor and a vertical transistor is providing conveniently the necessary isolation between the storage capacitor and the transistor.
SUMMARY OF THE INVENTION
In one aspect, the present invention is directed to a method for forming in a semiconductor body a memory cell that positions its storage node in a polysilicon-filled vertical trench and its transistor in part along a sidewall of the trench in a manner that results in better dielectric isolation between the storage capacitor and the transistor. A plurality of these memory cells are simultaneously formed in the semiconductor body to form a DRAM.
A key factor in the process is the use of the node dielectric layer as an oxidation barrier for the growth of an additional silicon oxide layer at the top of the trench for isolating the gate electrode of the transistor from the storage node. Another important factor is the use of a raised shallow trench filled with silicon oxide for better separating the gate conductor and the storage node.
In an illustrative embodiment, there is formed in a semiconductor body {e.g., a monocrystalline silicon body (substrate)} a deep vertical trench after which a relatively thick LOCOS type collar is formed along its upper portion and a silicon nitride storage node dielectric layer over the walls of the trench including the oxide collar. The trench is then filled with doped polysilicon after which a recess is formed at the top of the fill. Now the top portion of the remaining polysilicon fill is oxidized to form an oxide layer over the top of the trench polysilicon fill (the trench top oxide). Now the semiconductor body is exposed to a wet isotropic etch that bares the sidewalls of the top of the trench of any dielectric layer and also etches away a portion of the oxide collar surrounding the top of the polysilicon fill of the trench but leaves a portion of the trench top oxide layer stranded at the top of the polysilicon fill. Now there is deposited a layer of doped silicon over the top of the wafer including the trench for surrounding the sides of the stranded trench top oxide layer. This wall layer will provide the conductive strap linking the doped polysilicon fill of the trench and the source of the vertical transistor that will be formed along the sidewall of the trench. Now the surrounding silicon layer is largely stripped away to leave only a portion on the sidewall of the trench that surrounds the sides of the oxidation layer over the top of the trench polysilicon fill. This will serve the roles just mentioned. Now there is grown a new oxide layer over the semiconductor body including the trench top oxide. This new oxide layer will serve as the gate dielectric of the vertical transistor and to isolate further the previously-mentioned link silicon portion from the doped polysilicon that is now deposited over the top of the semiconductor body to fill the upper portion of the trench. This new polysilicon layer will provide the gate and the gate conductor of the vertical transistor. This gate conductor polysilicon layer is now patterned to provide space for the shallow trench that will be filled with silicon oxide that will provide isolation between the memory cells of the DRAM.
The rest of the process is essentially the same as in the shallow trench isolation prior art. The drain of the transistor is formed in the monocrystalline silicon adjacent the trench and the channel between the source and drain includes both a vertical portion in the bulk monocrystalline silicon along a sidewall of the trench and a horizontal portion in the top surface of the monocrystalline silicon.
Viewed from one aspect, the present invention is directed to a memory cell for use in a dynamic random access memory of the kind that uses a transistor and a storage capacitor in a semiconductor body. The memory cell comprises a relatively deep trench and a transistor. The trench has substantially vertical side walls that includes a deep portion that is filled with doped polysilicon, that is insulated from the semiconductor body by a dielectric layer and that serves as the storage node of the memory cell, the polysilicon fill also including an oxide layer at its top. The transistor includes a drain region that is part of the semiconductor body and a source region that lies in the semiconductor body along a sidewall at the top of the polysilicon fill of the deeper portion of the trench, and a channel region extending between the source and drain regions along the top surface of the semiconductor body and along a sidewall of the deep trench that includes vertical and horizontal portions, and a doped silicon gate conductor that fills the upper portion of the trench and is electrically insulated from the doped polysilicon in the deeper portion of the trench both by a dielectric layer that was formed at the top of the polysilicon fill in the deeper portion of the trench and a dielectric layer that was formed as part of the gate dielectric of the transistor.
REFERENCES:
patent: 6074909 (2000-06-01), Gruening
DeBrosse John
Gruening Ulrike
Mandelman Jack
Radens Carl
Braden Stanton C.
Infineon - Technologies AG
Lee Calvin
Smith Matthew
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