Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2000-06-26
2001-08-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S063000
Reexamination Certificate
active
06282116
ABSTRACT:
FIELD OF INVENTION
This invention relates to a dynamic random access memory (DRAM), and more particularly, to the layout and interconnection of the memory cells in a DRAM to increase the density of cells in the DRAM.
BACKGROUND OF THE INVENTION
There is a continuing trend towards increasing the capacity of DRAMs. Such an increase in capacity is best achieved by decreasing the surface area of the memory cells and increasing their packing density to increase the size of the array in the silicon chip that houses the DRAM.
Various techniques have been used to increase the packing density. One technique has been to use a vertical trench to form the capacitor that serves as the storage site of the cell.
Another technique has been to use as the switch transistor a vertical transistor formed on a sidewall of the vertical trench that provides the capacitor. Another technique has been to use a common drain and common bit line for a pair of switch transistors formed in a single active area that includes a pair of memory cells. Another technique is to form the storage capacitor of the cell as a stack of layers on the surface of the silicon chip. Other techniques have involved particular shapes and layouts for the active area of the cell to permit more efficient packing.
SUMMARY OF THE INVENTION
The invention provides a novel layout and interconnection pattern for the cells of the array that forms the DRAM. It is characteristic of the layout the cells are formed in clusters of four in a single active area. Each of the four transistors of the cluster has its own storage capacitor, advantageously a vertical trench capacitor. In such a case, the four transistors share a common base region in which are formed four separate channels, each advantageously a vertical channel extending along a side wall of a different vertical trench. Each transistor has its own source, advantageously buried in the base region, that electrically contacts an inner plate of its associated trench capacitor. The drains of the four transistors advantageously are merged at the top surface of the base region in a single surface layer so that a single bit line can address each of the four transistors of the cluster by way of such merged drain. A different word line connects to each of the four gates of the four transistors of the cluster. For achieving economy in the number of gate-word line connections, the gates of four different transistors, each from a different active area cluster, share a common contact to a word line. Advantageously this is done by providing a common contact layer to the gate conductors of the four transistors to be interconnected to the single word line.
To achieve the structure described, the active areas that house the four transistors of a cluster advantageously are formed in a cross-like shape with the four ends of the two crossbars the sites of the four vertical trenches. Advantageously, the active areas are isolated from one another by a shallow dielectric trench in the bulk of the semiconductive chip that houses the DRAM.
Preferably, the active areas are so disposed that each word line can be straight and still make an electrical connection to the gate conductors of four different transistors in four different active areas by way of a single contact. Additionally, the active areas preferably are so disposed that the bit lines can be straight and still make contact to the merged drain contact of the four transistors of a cluster by extending essentially perpendicularly to the word lines over the surface of the chip.
Alternatively, the storage capacitor can be a stacked capacitor over the surface of the chip in which case the switch capacitor is a horizontal or vertical transistor.
Viewed from a first aspect, the present invention is directed to a dynamic random access memory comprising a semiconductive chip in which there are formed a plurality of discrete active areas, each active area including a cluster of four switch transistors and four storage capacitors, each of the four transistors including a separate source and a separate gate and sharing a common drain and a common base region, the gate of each transistor being adapted to form in the base region a discrete channel extending between its source and the shared drain of its associated transistor and being connected to a associated word line, the source of each transistor being connected to the storage node of its associated storage capacitor, and the common drain of each transistor of a cluster being connected to a common bit line.
Viewed from a second aspect the present invention is directed to a memory cell cluster of four transistors for use in a dynamic random access memory that comprises an active area that is essentially cross-like in shape with two intersecting crossbars characterized in that each end of the two crossbars includes a vertical trench capacitor and that it includes a common base region between the trenches, said base region including four vertical transistors, each having its source and its drain positioned along a sidewall of a different trench and between which in operation a channel is induced, the four sources being isolated from one another by the base region, the four drains being merged together at the top surface of the base region.
Viewed from a third aspect the present invention is directed to a dynamic random access memory comprising a semiconductive chip in which there are formed a plurality of discrete active areas, each active area including a cluster of four switch transistors each having a gate and a drain and a source, and four storage capacitors each having first and second terminals, the four gates of the switch transistors in each cluster being connected to a common word line, each of the drains of the four transistors in each cluster being connected to three drains of switch transistors in three different clusters, the source of each switch transistor in a cluster being connected to the first terminal of its associated storage capacitor and the second terminal of its associated storage capacitor being adapated to be connected to a reference potential.
The invention will be better understood from the following more detailed description taken with the accompanying drawing.
REFERENCES:
patent: 6118683 (2000-09-01), Kunkel et al.
Butt Shahid
Kunkel Gerhard
Radens Carl J
Infineon Technologies North America Corp.
Nelms David
Ostroff Irwin
Tran M.
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