Dynamic random access memory

Details Dynamic random access memory Dynamic random access memory

1988-04-21

1990-07-31

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

36523001, 3652385, G11C 700, G11C 800

Patent

active

049455176

ABSTRACT:
A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal W having a shorter duration than that of the signal W at a down edge of the signal W as a trigger. The output signal W of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

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IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, S. 929-933.

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