Dynamic random access memory

Details Dynamic random access memory Dynamic random access memory

1997-12-09

1999-03-30

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Differential sensing

365149, G11C 1124

Patent

active

058897178

ABSTRACT:
An nMOS transistor 31 has a gate connected to a bit line *BL with its source and drain short-circuited and connected to a dummy word line DWL0. After setting the bit lines BL and *BL to a precharge potential Vpr=Vii/2, a transfer gate 11 is turned on. Next, the potential on the dummy word line DWL0 is raised from Vs=Vpr-Vth, where Vth is a threshold voltage of the nMOS 31, to Vii and then a sense amplifier 30 is set in an active state. If a pMOS transistor is employed in place of the nMOS transistor 31, its source and drain are short-circuited and connected to the bit line *BL with its gate connected to the dummy word line DWL0.

REFERENCES:
patent: 4504929 (1985-03-01), Takemae
patent: 4606010 (1986-08-01), Saito
patent: 5255235 (1993-10-01), Miyatake
patent: 5410509 (1995-04-01), Morita
patent: 5532963 (1996-07-01), Kushiyama et al.
patent: 5574694 (1996-11-01), von der Ropp

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