Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-04-02
2001-08-28
Yoo, Do Hyun (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S233100, C365S202000, C365S222000, C365S189040
Reexamination Certificate
active
06282606
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to electronic memories and in particular to dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, and systems and methods using the same.
BACKGROUND OF THE INVENTION
Dynamic random access memory (DRAM) is the principal type of memory used in most applications such as personal computers (PCS). When compared, for example, to static random access memory (SRAM), DRAM is less expensive, consumes substantially less power, and provides more bits in the same chip space (i.e. has a higher cell density). DRAM is normally used to construct those memory subsystems, such as system memories and display frame buffers, where power conservation and high cell density are more critical than speed. In most computing systems, it is these subsystems which dominate the system architecture, thus making DRAM the prevalent type of memory device on the market.
Notwithstanding these significant advantages, DRAMs are also subject to significant restraints due to the manner in which they must be constructed and operated. Specifically, since each cell stores data as charge on a capacitor (i.e. charged to a predetermined voltage for a logic 1 and discharged to approximately 0 volts for a logic 0), the length of time a bit, and in particular a logic 1 bit, can be stored in a given cell is a function of the ability of the capacitor to retain charge. Charge retention, and consequently data integrity is in turn a function of charge leakage.
Almost all DRAMs maintain data integrity through the periodic refresh of the memory cells storing logic 1 data, which has deteriorated in voltage as charge has leaked off the capacitor, back to the full logic 1 storage voltage. This is essentially done by performing read operations to the cell array on a row by row basis (the latching and restore functions of the sense amplifiers returning all voltages to their original levels). Depending on the refresh scheme, all the rows in the array or subarray may be refreshed by stepping though the rows in a single sequence or by distributing the refresh of smaller groups of rows of the array between read and write operations.
In the system environment, the need to refresh the system DRAM presents some substantial problems. In particular, during the period in which the DRAM is being refreshed, the processor, core logic, or controller managing the given memory, locks out all accesses to the memory from anywhere in the system. While the timing of the precharge period can be adjusted, for example by the CPU, to meet overall system needs, the maximum period between refreshes for a given device cannot be exceeded without the risk of data loss.
If the refresh can be “hidden”, the interface between the DRAM and the remainder of the system will emulate that of an SRAM. In other words, the system, with proper timing, can perform a continuous sequence of accesses to memory without periodic interruption for refresh. Given the criticality of the problem of refresh, a need has arisen to find efficient means of hiding refresh.
SUMMARY OF THE INVENTION
The present inventive concepts are embodied in a memory including an array of rows and columns of memory cells, with each column associated with a pair of complementary bitlines. An access sense amplifier is coupled to each pair of the complementary bitlines for sensing and latching data from cells along a selected row during a first portion of a random access cycle. A refresh sense amplifier is coupled to each pair of the complementary bitlines refreshing data from cells along a selected row during a second portion of the random access cycle.
An additional embodiment of these concepts is a memory system including a memory comprising an array of rows and columns of memory cells, with each column associated with a pair of complementary bitlines and first and second sense amplifiers coupled to each of the pairs of bitlines. Memory control circuitry from the first part of a random access cycle accesses selected cells in the array using the first sense amplifiers and during a second part of the random cycle uses the second sense amplifiers to refresh selected cells in the array.
A method is also disclosed for operating a dynamic random access memory using an array of memory cells arranged in rows and columns, with each column associated with a pair of complementary bitlines. During a first part of a random access cycle, data are sensed and latched from selected cells in the array using a first set of sense amplifiers coupled to the complementary pairs of bitlines. First set of sense amplifiers are isolated and the pairs of complementary bitlines precharged. During a second part of the random cycle, selected cells in the array are refreshed using a second set of sense amplifiers coupled to the complementary pairs of bitlines.
The present inventive concepts allow for read and refresh. Thus, the memory can be accessed on a continuous basis without interruption for refresh. In other words, a DRAM is provided having an SRAM-type interface to the processing components of the computing system.
REFERENCES:
patent: 4829484 (1989-05-01), Arimoto
patent: 5007022 (1991-04-01), Leigh
patent: 5511033 (1996-04-01), Jung
patent: 5627791 (1997-05-01), Wright et al.
patent: 5724296 (1998-03-01), Jang
patent: 5778237 (1998-07-01), Yamamoto et al.
McLean Kimberly
Murphy James J.
Silicon Aquarius, Inc.
Winstead Sechrest & Minick
Yoo Do Hyun
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