Dynamic RAM semiconductor memory and method for operating...

Details Dynamic RAM semiconductor memory and method for operating... Dynamic RAM semiconductor memory and method for operating...

2005-02-22

2005-02-22

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S230030

Reexamination Certificate

active

06859406

ABSTRACT:
A dynamic RAM semiconductor memory with a shared sense amplifier organization concept, in which the cell arrays are subdivided into blocks whose bit lines are connected in pairs from two adjacent blocks in each case to a common sense amplifier and the sense amplifiers are disposed between the cell blocks. In which case bit line switches are disposed in sense amplifier strips—lying between the blocks—between in each case two adjacent sense amplifiers in order to momentarily connect the other ends—not connected to the sense amplifiers—of two bit line pairs from the adjacent cell blocks during a precharge phase of a bit line pair activated directly beforehand. The precharge phase takes place at the start of a charge equalization phase.

REFERENCES:
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patent: 5740120 (1998-04-01), Okamura
patent: 5798975 (1998-08-01), Büttner et al.
patent: 6469951 (2002-10-01), Toda
patent: 20020067653 (2002-06-01), Toda
patent: 196 32 780 (1998-02-01), None

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