Dynamic RAM refresh circuit with DMA access

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3649649, 3649504, 364952, 3649481, 365222, G06F 1500, G06F 1200

Patent

active

048842346

ABSTRACT:
A semiconductor memory controller chip associated with a remote DMA device, a multispeed microprocessor and a DRAM memory requiring refreshing periodically includes refresh circuits for generating refresh signals for controlling refreshing of the memory during transparent and contention refresh operations. When a conflict occurs between the DMA device requesting access to the memory and the occurrence of a transparent refresh operation, control signals are generated to allow the memory to be refreshed prior to the time the DMA device is given access to the memory, thereby eliminating the need for a contention refresh operation. Control signals are also generated in accordance with the speed of the microprocessor for synchronizing the operation of the microprocessor with the operation of the DMA device.

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