Dynamic RAM provided with a defect relief circuit

Details Dynamic RAM provided with a defect relief circuit Dynamic RAM provided with a defect relief circuit

1998-03-05

1999-10-19

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36518907, G11C 700

Patent

active

059700017

ABSTRACT:
An X address buffer for generating an internal address signal by capturing an X address signal input from an address terminal is brought into an operating state before an external control clock is input. A redundancy address comparator for detecting a match/mismatch signal by comparing the generated internal address signal with a stored X-system defective address is used as a static circuit. Thereby, the redundancy address comparator starting operation is accelerated and as a result, acceleration of the reading operation is achieved.

REFERENCES:
patent: 5835436 (1998-11-01), Ooishi

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