Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1998-04-23
2000-03-07
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711105, 711152, 711163, 711164, G06F 1318
Patent
active
060353724
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to microprocessors, and more particularly to microprocessors for use in systems with Dynamic Random Access Memories (DRAMs).
BACKGROUND OF THE INVENTION
In many known processing systems there are several processors, or other circuits which include a processing unit (hereinafter referred to as masters), which are coupled to a common bus so that they can all access various slave devices also coupled to the bus, such as various types of memory devices, e.g. DRAMs, Static Random Access Memories (SRAMs), Read Only Memories (ROMs), or other types of peripheral devices, e.g. storage devices or communications interfaces. In some instances, however, a particular DRAM is only ever accessed by a single master device, so that it can be considered proprietary or private to that one master device.
The DRAMs are provided with Row Access Strobe (RAS) and Column Access Strobe (CAS) line inputs which are used for addressing a particular memory cell by its row and column address for both reading the cell and writing to the cell. A feature of the use of the RAS and CAS lines for addressing is that the RAS input is used to designate a so-called page of the DRAM, while the CAS input designates a particular location or address within that page, so that, as long as successive cells to be addressed are within the same page (so-called fast page mode), only the CAS input need be changed and the RAS input can remain asserted but does not need to be read each time, thus shortening the access cycle. This can only happen, of course, as long as the same master device has control of the bus, so that it can be sure that no other master device has accessed another page of the DRAM in between two of its accesses. Thus, every time the master device gains bus control, it must address using both RAS and CAS lines (so-called out-of-page access), which involves more time.
Furthermore, as is well known, DRAMs need to be refreshed in order for them to maintain the data in their memory cells, and this can be done by enabling first the CAS input and then the RAS input, instead of the RAS input first followed by the CAS input, as is done for addressing. Such refreshing needs to be done regularly so that the master device which controls the refreshing must obtain bus control, perform the refreshing and then relinquish control of the bus. This uses up valuable bus time, which could have been used by other master devices.
The present invention therefore seeks to provide a microprocessor for use with a private DRAM which overcomes, or at least reduces the above-mentioned problems of the prior art. The term "microprocessor" hereafter is intended to include all master devices.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a microprocessor having at least RAS and CAS outputs for exclusive coupling, via a bus, to RAS and CAS inputs of a private DRAM, the microprocessor comprising a DRAM Control Register having at least one bit which is set to designate whether the DRAM is private to the microprocessor, a read circuit which reads the one bit and determines whether the bit is set, and a control logic circuit coupled to the read circuit for controlling functions of the microprocessor according to whether the DRAM is private to it.
In one embodiment, the control logic circuit controls a DRAM refresh function of the microprocessor such that the microprocessor performs the DRAM refresh function using the RAS and CAS outputs without issuing a request for, nor assuming, control of the bus, when the one bit is set to indicate that the DRAM is private.
In another embodiment, the control logic circuit controls a DRAM addressing function of the microprocessor to allow the microprocessor to relinquish control of the bus without releasing the RAS and CAS lines, thereby allowing fast page mode access to the DRAM the next time the microprocessor has control of the bus, when the one bit is set to indicate that the DRAM is private.
According to a second aspect of the present
REFERENCES:
patent: 5394541 (1995-02-01), Chesley et al.
patent: 5448742 (1995-09-01), Bhattacharya
patent: 5649161 (1997-07-01), Andrade et al.
patent: 5737744 (1998-04-01), Callison et al.
patent: 5873114 (1999-02-01), Rahman et al.
Galanti David
Goren Avner
Zmora Eitan
Chan Eddie P.
Dover Rennie W.
Motorola Inc.
Nguyen Than
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