Static information storage and retrieval – Read/write circuit
Patent
1985-05-02
1990-10-02
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
365207, 365208, 365210, G11C 700, G11C 11404
Patent
active
049611666
ABSTRACT:
A dynamic RAM, in which the difference between a data signal level from one of a pair of complementary data lines coupled to a memory cell and a reference potential level of the other of the complementary data lines is differentially amplified by a sense amplifier. The data line taking the reference potential level is coupled to the other data line through a switch element so that its data line capacitance is increased. As a result, the reference potential level is held at a relatively stable level irrespective of a leakage current such as that caused by .alpha. particles. This construction makes it possible to use a full-size dummy cell because the capacitance of the data lines which takes the reference potential level is increased. The reference potential level achieved by the use of the full-size dummy cell is made relatively accurate because of the relative accuracy between the capacitances of the memory cells and the capacitance of the full-size dummy cell.
REFERENCES:
patent: 4351034 (1982-09-01), Eaton, Jr. et al.
patent: 4363111 (1982-12-01), Heightley et al.
patent: 4443868 (1984-04-01), Takemae
patent: 4551820 (1985-11-01), Matsuura
patent: 4559619 (1985-12-01), Ikeda
patent: 4602355 (1986-07-01), Watanabe
"Storage Array and Sense/Refresh Circuit for Single-Transistor Memory Cells", by Karl U. Stein et al., appearing in the IEEE Journal of Solid State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 336-340.
Ono Kunio
Sato Katsuyuki
Yanagisawa Kazumasa
Bowler Alyssa H.
Hitachi , Ltd.
Popek Joseph A.
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