Dynamic ram device having high read operation speed

Details Dynamic ram device having high read operation speed Dynamic ram device having high read operation speed

1994-11-02

1996-11-12

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365190, 365208, 365222, G11C 706

Patent

active

055746969

ABSTRACT:
In a dynamic random access memory device including a plurality of word lines, a plurality of bit lines, and a plurality of dynamic memory cells connected to the word lines and the bit lines, a switching circuit is provided between one pair of the bit lines and one sense amplifier, and a switching amplifier is provided between one pair of the bit lines and a read amplifier. Before the connection of the sense amplifier by the switching circuit to the pair of the bit lines, the read amplifier is connected by the switching amplifier to the pair of the bit lines.

REFERENCES:
patent: 4479202 (1984-10-01), Uchida
patent: 4504748 (1985-03-01), Oritani
patent: 4507759 (1985-03-01), Yasui et al.
patent: 5058072 (1991-10-01), Kashimura
patent: 5295103 (1994-03-01), Yamauchi

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