Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1993-12-21
1995-03-28
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Data refresh
36518901, 365227, G11C 1300
Patent
active
054023840
DESCRIPTION:
BRIEF SUMMARY
Technical Field of the Invention
The present invention relates to a refresh switching circuit for a dynamic RAM (Random Access Memory) such as that commonly used as the memory device for a personal computer.
BACKGROUND OF THE INVENTION
A main memory device in a personal computer includes for general use thereof a dynamic RAM which is advantageous in view of the unit cost thereof in a memory capacity. Memory capacities of semiconductors are increased with the technical progress thereof, thereby reducing the size of personal computers.
A dynamic RAM is needed to be routinely refreshed for holding any data stored therein.
Conventional personal computers employ a RAS (Row Address Strobe)-only refresh procedure as a most standard technique wherein a CAS (Column Address Strobe) signal is set to a high level and a RAS signal is varied in conformity with refresh addresses applied to an address terminal, and refresh is achieved by selecting all refresh addresses. The RAS-only refresh procedure is a common refresh technique for systems using dynamic RAMs.
The RAS signal serves to latch a row address supplied from the outside to select the row of a memory cell of a dynamic RAM in an internal row address decoder.
The CAS signal serves to latch a column address supplied from the outside to select the column of a memory cell of a dynamic RAM in an internal column address decoder.
With reference to the accompanying drawings, the read/write operation of a dynamic RAM and the RAS-only refresh procedure will be described.
As illustrated in FIG. 1, a central processing unit (hereinafter referred to as a CPU) 401 reads data from and writes data into a dynamic RAM array 411. Although a system logic control unit is typically considered part of the CPU, the system logic will be referred to separately to facilitate an understanding of the read/write and refresh procedures for the dynamic RAM. The CPU 401 provides a read or write address to a CPU address bus 405 and further provides a CPU status signal 403 to instruct a system logic 406 to read/write the data from/into the dynamic RAM array 411.
The system logic 406 transmits the address provided from the CPU address bus 405 onto a memory address bus 407 as a row address and a column address of the dynamic RAM.
The system logic 406 further switches the RAS signal 408 from a "H" level to a "L" level while providing the row address, thereby latching that signal in the dynamic RAM array 411 as the row address of the dynamic RAM.
Thereafter, the system logic 406 switches the CAS signal 409 from a "H" level to a "L" level while providing the column address,, thereby latching that signal in the dynamic RAM array 411 as the column address of the dynamic RAM.
At that time, if the CPU status signal 403 from the CPU 401 is an instruction to write associated data into the dynamic RAM, a WE (Write Enable) signal 410 is switched from "H" to "L" level, thereby transferring the write data on the CPU data bus 402, provided from the CPU 401, into the dynamic ]RAM array 411.
In contrast, if the CPU status signal 403 from the CPU 401 is an instruction to read associated data from the dynamic RAM, then after a short delay, data from the dynamic RAM array 411 is outputted on the CPU data bus 402 and is received by the CPU 401. The system logic 406 coordinates the timing of the receiving of the read data by the CPU 401 via a ready signal 404.
The foregoing is a description of the read/write operation by the CPU 401 from/into the dynamic RAM array 411.
The system logic 406 must refresh the dynamic RAM array 411 within a predetermined time interval while the CPU 401 reads/writes associated data from/into the dynamic RAM array 411.
The system logic 406 includes therein a circuit for generating raw addresses, which serves to interrupt the CPU 401 during each predetermined time interval by providing a row address for output to the memory address bus 407 while the RAS signal 408 is switched from the "H" level to the "L" level, maintaining the CAS signal 409 at the "H" level.
The aforementioned refreshing
REFERENCES:
patent: 5021951 (1991-06-01), Baba
Citizen Watch Co. Ltd.
Fears Terrell W.
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