Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-07-05
2002-02-19
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S039000, C326S041000, C326S113000
Reexamination Certificate
active
06348812
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to dynamic programmable logic arrays (DPLAs) and specifically to a DPLA that can be reprogrammed
BACKGROUND OF THE INVENTION
Dynamic programmable logic arrays (DPLAs) are utilized extensively. As shown in
FIG. 1
, a DPLA
5
includes input signals
2
to an AND plane
10
whose outputs
18
are then the inputs to an OR plane
14
that produces the output signals
20
. The outputs of the AND plane
10
are known as AND term signals (Al to Am). The outputs of the OR plane are known as OR term signals (O
1
to On).
FIG. 1
shows k number of inputs, m number of AND term signals, and n number of OR term signals. The AND plane
10
further comprises multiple NOR term generators
12
, each of which outputs a wired-NOR signal
18
that is first precharged to Vcc (the supply voltage) and then conditionally discharged to GND (the ground voltage). The Vcc and GND can represent high (TRUE) and low (FALSE) logic states, respectively. Similarly, the OR plane
14
also comprises multiple NOR term generators
16
, each of which outputs a wired NOR signal
20
that is first charged to high logic level and then conditionally discharged to low. logic level. For simplicity, the clocks that control the precharge and discharge are not shown in FIG.
1
.
FIG. 2
shows two NOR term generators
12
in the AND plane. The wired-NOR signal
30
is discharged if one or more input signals
2
that are “programmed” to affect this output signal are high. An input signal
2
is programmed to affect an output signal by providing an evaluate circuitry
32
controlled by the input signal
2
.
FIG. 2
shows that the input signals I
1
and I
2
are programmed to affect the AND term signals Al and A
2
. If the evaluate circuitry labeled
34
were not provided, for example, then the input signal I
1
cannot affect the AND term signal A
1
while it still affects the AND term signal A
2
.
FIG. 3
shows a conventional evaluate circuitry
38
for DPLA and the precharge transistor
40
and the discharge transistor
42
for the AND term signal. This precharge and conditional discharge circuitry is controlled in two non-overlapping phases, known as precharge and evaluate. During the precharge phase, both CLKP and CLKD are held low so that precharge transistor
40
is turned on and the discharge transistor
42
is turned off, forcing the output signal NL to be high. During the evaluate phase, both CLKP and CLKD are held high so that the precharge transistor
40
is turned off and the discharge transistor
42
is turned on. During the evaluate phase, if the input signal
46
is high to turn on the evaluate transistor
44
, then the charge stored at the output signal NL is discharged via the transistors
44
and
42
, resulting in the signal NL being low. If on the other hand, if the input signal
46
is low during the evaluate phase, the evaluate transistor
44
is turned off and the charge stored at the output signal NL remains high. The input signal
46
must not change during the evaluate phase to avoid falsely discharging the output signal NL.
A NOR term generator
12
, which comprises one precharge transistor and one discharge transistor and one evaluate circuitry, works as follows. During the precharge phase, the precharge transistor
40
is turned on and the discharge transistor
42
is turned off, forcing the output signal NL to be high. During the evaluate phase, the precharge transistor
40
is turned off and the discharge transistor
42
is turned on. During the evaluate phase, if one or more input signals that are programmed to affect this output are high, the charge stored at the output signal is discharged and NL becomes low. If none of the input signals are high, then there is no path for the charge stored at NL to be discharged and the NL remains high. The NOR term generators
16
in the OR plane
14
works as same as those in the AND plane
10
.
A detailed description of DPLA can be found in “Principles of C-MOS VLSI Design” by N. H. Weste and K. Eshraghian, Addison-Wesley, 2
nd
Edition, 1993, Chapter 8, pages 592-602 or in the U.S. Pat. No. 4,769,562.
Accordingly, a DPLA produces a predetermined set of outputs for a given set of inputs. Each output is a sum-of-products of a subset of the inputs. The DPLA implements the sum-of products functions by precharging and discharging wired-NOR circuits that are built within the array. These functions are programmed when a dynamic PLA is built such that the array can only produce the same set of output signals for a given set of input signals. A dynamic PLA is “programmable” only in the sense that it is easy to implement desired functions within the array when the array is built but not in the sense that the array can be programmed to provide different functions once the array is built. Therefore, if a different function is desired the DPLA is inflexible and must be replaced after being programmed.
Accordingly, what is needed is a system and method that overcomes the above mentioned problems. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A dynamic PLA (DPLA) that combines registers and dynamic PLA to make the array “reprogrammable” after the array is built is disclosed. The DPLA comprises at least one logic plane; and at least one reprogrammable evaluate module within the at least one logic plane. The at least one reprogrammable evaluate module includes a first program input, a second program input and a storage element coupled to the first and second program inputs, and an input pass transistor whose gate is coupled to the output of the storage element and whose source and drain are coupled to a control input and the gate of an evaluate transistor. The storage element is written by placing a desired value on one of the first and second program inputs and asserting a signal at the other of the first and second program inputs.
A system and method in accordance with the present invention provides a dynamic PLA which is reprogrammable. In such a DPLA, the AND plane and OR plane are fully populated with reprogrammable evaluate modules such that every input signal can be programmed to affect every AND term output and every AND term signal can be programmed to affect every OR term output. In so doing, the DPLA can be reprogrammed after a device is built to allow for a change in functionality of the device.
REFERENCES:
patent: 4995004 (1991-02-01), Lee
patent: 5559449 (1996-09-01), Padoan et al.
patent: 5568062 (1996-10-01), Kaplinsky
patent: 5812792 (1998-09-01), Haddock et al.
patent: 6262597 (2001-07-01), Bauer et al.
patent: 58147236 (1983-09-01), None
IBM Technical Disclosure Bulletin, Feb. 1992, vol. 34, Issue 9, pp. 158-159.
Elan Research
Paik Steven S.
Sawyer Law Group LLP
Tokar Michael
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