Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-11-28
2006-11-28
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C710S244000
Reexamination Certificate
active
07143242
ABSTRACT:
A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.
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Bachand Derek T.
Hill David L.
Marr Deborah T.
Prudvi Chinna B.
Baker Paul
Kenyon & Kenyon LLP
Padmanabhan Mano
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