Dynamic predecoder circuitry for memory circuits

Details Dynamic predecoder circuitry for memory circuits Dynamic predecoder circuitry for memory circuits

2000-08-29

2003-07-22

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C326S108000, C326S105000, C327S208000, C365S203000, C365S230060

Reexamination Certificate

active

06597201

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to dynamic predecoder circuitry and particularly to dynamic predecoder circuitry for use in array decoding for integrated circuit memory chips.
Decoding circuitry is common in memory circuits to enable a particular row and/or a particular column for reading and/or writing. To eliminate the amount of circuitry required to perform the decoding functions, which translates into less silicon area being used, decoding circuitry often includes predecoder circuitry. Although useful for certain, limited applications, conventional predecoder circuits typically have several drawbacks.
A first common drawback of conventional predecoder circuits is that they are relatively slow. In particular, conventional predecoder circuits use static logic gates, typically full CMOS gates, which are relatively slow. As will be appreciated by those skilled in the art, speed is always a factor in memory circuit design. Slower predecoder circuitry translates into slower memory circuit performance.
A second common drawback of conventional predecoder circuits is that they require a relatively large chip area. In particular, conventional predecoder circuits use full CMOS logic gates, which requires additional chip area. As will be appreciated by those skilled in the art, decreasing the chip area required for circuits included within a memory circuit translates into increased performance and reduction in costs associated with memory circuits.
A third common drawback of conventional predecoder circuits is that they consume a relatively large amount of power. This is particularly due to use of full CMOS gates in conventional predecoder circuits. As will be appreciated by those skilled in the art, generally speaking, the less power consumed by a memory circuit, the better.
A fourth common drawback of conventional predecoder circuits is that they require separate address busses for each memory bank. This requires a relatively large amount of chip area, which translates into increased chip size for the memory circuit.
Two conventional predecoder circuits will now be briefly described. Referring to
FIG. 1
, illustrated therein is a conventional row predecoder circuit
10
and a conventional row decoder circuit
12
, both of which are typically used in the prior art. As shown and as will be appreciated by those skilled in the art, row predecoder circuit
10
includes several devices that are not used in the embodiments of the row predecoder circuits of the present invention shown in
FIGS. 3 and 5
, respectively. Further, the row predecoder circuit
10
of
FIG. 1
does not permit sharing of the row address bus. Accordingly, separate address busses must be used for each memory bank. The additional devices and the additional address busses inherently increase the memory circuit chip size, which is a drawback.
FIG. 2
illustrates another conventional row predecoder circuit
20
and the conventional row decoder circuit
12
shown in FIG.
1
. Row predecoder circuit
20
includes a full CMOS NAND gate
22
and an inverter
24
. As shown and as will be appreciated by those skilled in the art, by incorporating full CMOS NAND gate
22
, row predecoder circuit
20
uses static logic, as opposed to dynamic logic. Predecoder circuit
20
is relatively slow in comparison to the embodiments of the present invention shown in
FIGS. 3 and 5
, respectively. The full CMOS logic gate takes up a larger silicon area than the CMOS gates shown in
FIGS. 3 and 5
. The full CMOS logic technology also consumes higher power due to increased loading and the consequent through current during gate switching.
In light of the foregoing, it is an object of the preferred forms of the present invention to provide for a relatively fast predecoder circuit.
It is another object of the preferred forms of the present invention to provide for a predecoder circuit that requires a relatively small amount of chip area.
It is still another object of the preferred forms of the present invention to provide for a predecoder circuit that consumes a relatively small amount of power.
It is yet another object of the preferred forms of the present invention to provide for a predecoder circuit that allows for a shared address bus for multiple memory cell banks in a memory circuit.
It is still yet another object of the preferred forms of the present invention to provide for a predecoder circuit that uses dynamic gates to provide for faster speed and little or no through current during switching.
These and other objects of the preferred forms of the invention will become apparent from the following description. It will be understood, however, that an apparatus could still appropriate the invention claimed herein without accomplishing each and every one of these objects, including those gleaned from the following description. The appended claims, not the objects, define the subject matter of this invention. Any and all objects are derived from the preferred forms of the invention, not necessarily the invention in general.
Throughout this specification, reference will be made to inputs, outputs, lines and busses that are included within the preferred form of the dynamic predecoder circuitry. Throughout this specification, if reference is made to one of these, such as a line, and that line is given a particular reference numeral for identification purposes, then another data line given the same reference numeral but with a “B” designation shall be understood to be its complement. For instance, a line
300
B would be understood to be the complement of line
300
. Conversely, line
300
would be the complement of line
300
B. Generally speaking, if they are not tied together (such as when they are equalized), or if they are not driven to the same logic state for a special purpose, when line
300
is HIGH, line
300
B is LOW. Conversely, absent special conditions, when line
300
is LOW, line
300
B is HIGH. Those skilled in the art will appreciate this concept and understand this designation hereby incorporated herein by reference.
SUMMARY OF THE INVENTION
In a preferred form, the present invention is directed to a predecoder circuit for use in association with a memory circuit. The predecoder circuit includes a dynamic NAND gate comprising first and second NMOS transistor devices coupled in series. The first NMOS transistor device has a control electrode to which a bank active select signal is applied. The second NMOS transistor device has a control electrode to which a row address selection signal is applied. The predecoder circuit further includes a precharge circuit coupled to one of the first and second NMOS transistor devices defining a junction between the precharge circuit and the one of the first and second NMOS transistors. The precharge circuit includes a PMOS transistor device having a control electrode to which a precharge signal is applied. The predecoder circuit also includes a first inverter having an input terminal electrically coupled to the dynamic NAND gate and the precharge circuit at the junction and an output terminal selectively electrically connectable to at least one row decoder circuit for said memory circuit. The predecoder circuit further includes a second inverter having an input terminal electrically coupled to the output terminal of the first inverter and an output terminal electrically coupled to the input of the first inverter.
In another preferred form, the present invention is again directed to a predecoder circuit for use in association with a memory circuit. In this preferred form, the predecoder circuit includes a dynamic NAND gate comprising first and second NMOS transistor devices coupled in series. The first NMOS transistor device has a control electrode to which a bank active select signal is applied. The second NMOS transistor device has a control electrode to which a row address selection signal is applied. The predecoder circuit also includes a precharge circuit coupled to one of the first and second NMOS transistor devices defining a junction between the precharge circu

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