Dynamic precharge redundant circuit for semiconductor memory dev

Details Dynamic precharge redundant circuit for semiconductor memory dev Dynamic precharge redundant circuit for semiconductor memory dev

1999-10-28

2000-12-26

Elms, Richard

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 3651895, G11C 700

Patent

active

061669741

ABSTRACT:
A dynamic precharge redundant circuit for a semiconductor memory device. A PMOS transistor, a fuse, a first, second and third inverters, a first switch and a second switch are applied. A source of the PMOS transistor is coupled to a voltage supply, while a gate of the PMOS transistor is to receive a precharge signal. The fuse has a ground terminal and a terminal coupled to the drain of the PMOS transistor of which the drain is further coupled to an input terminal of the first inverter. The fuse is also coupled to a column address signal. The first inverter has an output terminal coupled to an input terminal of the first switch. The second inverter has an input terminal coupled to an output terminal of the first switch and an output terminal coupled to an input terminal of the third inverter, so as to output a bit-switch control signal. An input terminal of the second switch is coupled to an output terminal of the third inverter, while an output terminal of the second switch is coupled to both the output terminal of the first switch and the input terminal of the second inverter. Thus, an error caused by the generation of an interference signal of the bit-switch control signal is prevented, so as to prevent from damaging data of the bit line sense amplifier.

REFERENCES:
patent: 5583463 (1996-12-01), Merritt
patent: 5841708 (1998-11-01), Nagata
patent: 6052767 (2000-04-01), Matuki

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