Dynamic power management in a processor design

Details Dynamic power management in a processor design Dynamic power management in a processor design

2008-07-15

2008-07-15

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S322000, C713S324000

Reexamination Certificate

active

07401242

ABSTRACT:
A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.

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