Dynamic power and clock-gating method and circuitry with...

Details Dynamic power and clock-gating method and circuitry with... Dynamic power and clock-gating method and circuitry with...

2005-01-13

2009-02-03

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S320000

Reexamination Certificate

active

07487374

ABSTRACT:
Power-gated circuitry is put in a “sleep mode” that selectively gates both the power supply rails for static power control and the clock distribution for dynamic power control. A time interval M is established following a wake-up signal that includes the time to power-up, perform a computation, and return a result to the following circuitry. Likewise, a time interval N is established that indicates how long to wait after a result is returned before the power-gated circuitry is returned to the sleep mode to assure a desired performance. When a power-gated circuit is going to be needed for a future computation, it is issued a wake-up signal and a predetermined estimated time K for receipt of a next wake-up signal. A decision is made by analyzing the times M, N, and K as to when to return a power-gated circuit to the sleep mode following activation by a wake-up signal.

REFERENCES:
patent: 5400190 (1995-03-01), Miura
patent: 5481733 (1996-01-01), Douglis et al.
patent: 5774292 (1998-06-01), Georgiou et al.
patent: 6553501 (2003-04-01), Yokoe
Zhigang Hu et al. “Microarchitectural Techniques for Power Gating of Execution Units,”IBM T.J. Watson Research Center, 2004, pp. 32-37.

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