Dynamic phase selector phase locked loop circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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375376, 327158, 327159, 331 11, 331 25, 331 57, H03D 324

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active

056469683

ABSTRACT:
A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

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32Mb/s Read channel electronics, AD899 Preliminary datasheet Analog devices Inc. confidential, Version 0.5.4.
Welland et al, "Implementation of a Digital Read/Write Channel with EEPR4 Detection", IEEE Transactions on Magnetics, vol. 31, No. 2, pp. 1180-1185.

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