Dynamic phase assignment optimization using skewed static...

Details Dynamic phase assignment optimization using skewed static... Dynamic phase assignment optimization using skewed static...

2007-07-17

2007-07-17

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S097000

Reexamination Certificate

active

11015513

ABSTRACT:
A primarily domino logic block uses static buffers instead of clocked domino buffers to correct a phase skipping problem, while realizing the same logic function with less integrated circuit area, power consumption, and cost. The use of static buffers simplifies the clock network and clock tree synthesis. A domino logic circuit including at least one logic gate including a fast input and a slow input, and a static buffer inserted in series with the fast input of the logic gate. The falling time of the static buffer is set to be greater than a defined minimum falling time and less than a defined maximum falling time.

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