Multiplex communications – Wide area network – Packet switching
Patent
1990-05-10
1994-01-25
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 8513, 370 8514, H04L 1256, H04L 1246
Patent
active
052822010
ABSTRACT:
A digital data communications apparatus includes first and second processing groups, each made up of a plurality of processing cells interconnected by an associated bus. An element (RRC) transfers information packets generated by the processing cells between the first and second processing groups. The RRC includes an input for receiving packets from the bus of the first processing group, as well as first and second outputs for outputting packets to the buses of the first and second groups, respectively. A control element routes packets received at the input to a selected one of the outputs based upon a prior history of routings of the datum referenced in that information packet (or requests for that data) between said first and second processing groups.
REFERENCES:
patent: Re28811 (1976-05-01), Pierce
patent: 3723976 (1973-03-01), Alvarez et al.
patent: 3731002 (1973-05-01), Pierce
patent: 4358823 (1982-11-01), McDonald
patent: 4432057 (1984-02-01), Daniell et al.
patent: 4468733 (1984-08-01), Oka et al.
patent: 4510492 (1985-04-01), Mari et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4706080 (1987-11-01), Sincoskie
patent: 4714990 (1987-12-01), Desyllas et al.
patent: 4758946 (1988-07-01), Shar et al.
patent: 4780873 (1988-10-01), Mattheyses
patent: 4792895 (1988-12-01), Tallman
patent: 4811009 (1989-03-01), Orimo et al.
patent: 4864495 (1989-09-01), Inaba
patent: 4885742 (1989-12-01), Yano
patent: 4888726 (1989-12-01), Struger et al.
patent: 4972338 (1990-12-01), Crawford
patent: 4980816 (1990-12-01), Fukuzawa et al.
patent: 5006978 (1991-04-01), Neches
patent: 5025366 (1991-06-01), Baror
patent: 5055999 (1991-10-01), Frank et al.
patent: 5060186 (1991-10-01), Barbagelata et al.
patent: 5101402 (1992-03-01), Chiu et al.
patent: 5119481 (1992-06-01), Frank et al.
Lovett et al., Proceedings '88 Int'l. Conf. on Parrell Proc., v. 1, Penn State Univ. Press (Conf. Aug. 15-19, 1988) pp. 303 et seq.
Kai Li et al., Proceedings '89 Int'l. Conf. on Parallel Processing, Penn State Univ. Press (Conf. Aug. 8-12, 1989) pp. I-125 et seq.
Papamarcos et al., Proc. of 11th Annual Symposium on Computer Architecture (Conf. Jun. 5-7, 1984) pp. 348 et seq (IEEE).
"High Performance/High Availability Interprocessor Communication Method," IBM Technical Disclosure Bulletin, vol. 31, No. 2, Jul. 1988 pp. 41-42.
Schwartz, Telecommunications Network, "Introduction & Overview" pp. 1-20, Layered Architectures in Data Networks pp. 71-117.
Haridi et al, "The Cache Coherence Protocol of the Data Diffusion Machine" Parallel Architectures Proceedings, vol. I, pp. 1-18 (1989).
Proc. of the 6th Annual Phoenix Conf. on Computer and Communications, Feb. 25-27, 1987, pp. 14-17.
European Search Report for EP 91 30 4493.
"Multi-Microprocessors: an Overview . . . ," IEEE vol. 26 #2, pp. 216-228.
"Cm*--A Modular Multi-Microprocessor," Nat'l Comp Confr '77, 637-644.
Ciepielewsik et al., "A Formal Model for Or-Parallel . . . ", Proc. of the IFIP 9th World Computer Congress (1983) pp. 299-305.
Censier et al., "A New Solution to Coherence . . . ", IEEE Transaction on Computers, vol. c-27, No. 12 (Dec. 1978) pp. 1112-1118.
Eggers et al., "Evaluating the Performance of Four . . . ", Proc. of the 16th Annual Int'l Symposium on Computer Archit. (1989) pp. 2-15.
Gehringer et al., "The Cm* Hardware Architecture", Parallel Proc. the Cm* Experience, Digital Press, pp. 11-28, 432, 438.
Goodman et al., "The Wisconsin Multicube: A New . . . ", Proc. of the 15th Annual Int'l Symposium on Computer Archit. (1988) pp. 422-431.
Wilson, Sr. Editor, "Increased CPU Speed Drives Changes in Multiprocessor Cache and Bus Designs", Computer Design, (Jun. 1987) p. 20.
Ali et al., "Global Garbage Collection for Distributed . . . ", Int'l Jo. of Parallel Programming, vol. 15, No. 5 (1986) pp. 339-387.
Mizrahi et al., "Introducing Memory into the Switch . . . ", Proc. of the 16th Annual Int'l Symposium on Computer Archit. (1989) pp. 158-166.
Pfister et al., "The IBM Research Parallel Processor . . . ", IEEE Proc. of the 1985 Int'l Conf. on Parallel Proc. (1985) pp. 764-771.
Tabak, "Chapter 8 Bus-Oriented Systems", Multiprocessors, Prentice Hall (1990) pp. 92-102.
Warren et al, "Data Diffusion Machine-A Scalable . . . ", Proceedings of the International Conference on Fifth . . . , 1988, pp. 943-952.
Hagersten, "Some Issues on Cache-Only Memory Architecture," Scalable Shared-Memory Multiprocessors. May 1990. p. 12.
Hagersten et al, "The Data Diffusion Machine and its Data Coherency Protocols", Proceedings of the IFIP, pp. 127-148 (1990).
Binder Paul A.
Burkhardt, III Henry
Epstein David I.
Frank Steven J.
Kelly Dana R.
Kendall Square Research Corporation
Kizou H.
Olms Douglas W.
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