Dynamic on-die termination launch latency reduction

Details Dynamic on-die termination launch latency reduction Dynamic on-die termination launch latency reduction

2005-12-07

2008-03-11

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S032000, C326S034000

Reexamination Certificate

active

07342411

ABSTRACT:
Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination resistance circuit to provide a termination resistance for the I/O circuit. The integrated circuit may further include control logic to establish an initial termination resistance during a preamble associated with the command. Other embodiments are described and claimed.

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U.S. Appl. No. 11/171,625; Inventor: Hsien-Pao Yang; filed Jun. 30, 2005.
Office Action dated May 2, 2007 for corresponding U.S. Appl. No. 11/296,950, filed Dec. 7, 2005, to Cox et al.

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