Dynamic offset compensation based on false transitions

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data pulse evaluation/bit decision

Reexamination Certificate

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C714S002000, C714S048000, C714S704000, C714S705000, C714S713000, C714S724000, C714S745000, C714S798000, C714S817000, C714S818000, C714S819000, C375S316000, C370S395610, C370S497000, C327S040000

Reexamination Certificate

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07370247

ABSTRACT:
A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detector.

REFERENCES:
patent: 4535459 (1985-08-01), Hogge, Jr.
patent: 6002723 (1999-12-01), Chethik
patent: 6847789 (2005-01-01), Savoj
patent: 6909852 (2005-06-01), Cao
patent: 7016613 (2006-03-01), Savoj
patent: 7190906 (2007-03-01), Cao
patent: 7209525 (2007-04-01), Laturell et al.
patent: 2004/0268190 (2004-12-01), Kossel et al.
patent: 356169479 (1981-12-01), None
“10 Gbit/s Receiver, CDR and DeMUX GD16544”,Data Sheet Rev.:06, (Giga—an Intel Company), (2001), 17 pgs.
“2.5 Gbit/s Clock and Data Recovery GD16522”,Data Sheet Rev.: 21, (Giga—an Intel Company), (2001), 12 pgs.
“2.5 Gbit/s Clock and Data Recovery GD16547”,Data Sheet Rev.: 12, (Giga—an Intel Company),(2001), 9 pgs.
“2.5 Gbit/s Transponder Chip Set with Digital “Wrapping” GD16556/GD16557”,Data Sheet Rev.: 23, (Giga—an Intel Company), (2002), 28 pgs.
“Intel® LXT16725—10gbps 1:1 Signal Conditioning Transceiver for XFP Optical Applications”,Intel® Product Brief, Order No. 301482-001, (2004), 7 pgs.
Hsieh, M.-T., et al., “Clock and Data Recovery With Adaptive Loop Gain for Spread Spectrum SerDes Applications”,IEEE International Symposium on Circuits and Systems(ISCAS 2005), (2005), 4883-4886.
Lee, M.-J. E., et al., “CMOS High-Speed I/O's—Present and Future”,Proceedings of the 21st International Conference on Computer Design(ICCD '03), (2003), 8 pgs.
Musa, F. A., et al., “Clock Recovery in High-Speed Multilevel Serial Links”, [online]. Department of Electrical and Computer Engineering, University of Toronto. [archived Dec. 16, 2004]. Retrieved from the Internet: <URL: http://web.archive.org/web/20041216020641/http://www.eecg.utoronto.ca/˜tcc/ssmmse—slides.pdf>, 16 pgs.
Perrott, M. H., “6.076 High Speed Communication Circuits and Systems; Lecture 21—MSK Modulation and Clock and Data Recovery Circuits”,MITOPENCOURSEWARE, (Massachusetts Institute of Technology),(2003), 43 pgs.
Perrott, M. H., “PLL Design Using the PLL Design Assistant Program”, (Microsystems Technology Laboratories, Massachusetts Institute of Technology), (Apr. 2, 2005), 33 pgs.

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