Dynamic NOR gates for NAND decode

Details Dynamic NOR gates for NAND decode Dynamic NOR gates for NAND decode

1997-12-19

2000-06-27

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326105, 326103, H03K 19003

Patent

active

060811366

ABSTRACT:
A NOR gate pair includes a first and second NOR gate, each with a plurality of inputs and an output. A first NAND gate has a first input coupled to the output of the first NOR gate, a second input coupled to the output of the second NOR gate through a first input inverter, and an output. A second NAND gate has a first input coupled to the output of the second NOR gate, a second input coupled to the output of the first NOR gate through a second input inverter, and an output. A first output inverter is coupled to the output of the first NAND gate and a second output inverter is coupled to the output of the second NAND gate. This configuration assures that NOR gates used in a one-hot-decode decoder will all have logic-low outputs during a precharge phase.

REFERENCES:
patent: 5023838 (1991-06-01), Herbert
patent: 5144582 (1992-09-01), Steele
patent: 5606269 (1997-02-01), Pontius et al.
patent: 5909567 (1999-06-01), Novak et al.

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