Dynamic non-coherent cache memory resizing mechanism

Details Dynamic non-coherent cache memory resizing mechanism Dynamic non-coherent cache memory resizing mechanism

1997-02-03

1998-05-12

Lane, Jack A.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711 5, G06F 1200

Patent

active

057522553

ABSTRACT:
A dynamic cache resizing mechanism permitting a non-coherent cache memory to be altered in size during the operation thereof. A cache utilization monitoring system determines whether the cache size is optimised for a particular application and environment, and if it is not, modifies a selection process to resize the cache address space. The non-coherent property of the cache is utilized to permit the change of selection process during use, and the choice of selection process may be effected to take into account the proportion of live cache entries which will remain accessible after resizing, and the proportional change in size of the cache during a resizing operation.

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