Dynamic node keeper system and method

Details Dynamic node keeper system and method Dynamic node keeper system and method

2007-05-22

2007-05-22

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S121000, C365S189050

Reexamination Certificate

active

11199950

ABSTRACT:
The present invention system and method provides voltage level support for an output target signal (e.g., a dynamic node output signal) that “keeps” the output target signal at a particular voltage level with efficient suspension of the voltage level maintenance or support during an evaluation transition period (e.g., a read operation) of the output target signal.

REFERENCES:
patent: 5440243 (1995-08-01), Lyon
patent: 6690604 (2004-02-01), Hsu et al.
patent: 2003/0001623 (2003-01-01), Alvandpour et al.
Staslak et al., “WA 17.1 A 2nd Generation 440ps SOI 64b Adder”, 2000 IEEE International Solid-State Circuits Conference, ISSCC 2000/SESSION 17/Logic And Systems/Paper WA17.1, pp. 288-289, 2000.

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