Dynamic MOS random access memory

Details Dynamic MOS random access memory Dynamic MOS random access memory

1983-03-10

1985-10-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

365203, G11C 700

Patent

active

045492840

ABSTRACT:
A dynamic random access memory, which is accessed in response to an address strobe signal, has an automatic refresh circuit which consists of a clock generator that generates refresh clock pulses when the address strobe signal is not produced, and an address counter that increments a refresh address by counting the refresh clock pulses. Information retained in memory cells is automatically refreshed by an operation of the automatic refresh circuit. The dynamic random access memory of this arrangement does not need a special external terminal for the refresh operation and an external circuit associated therewith. Thus, the random access memory of this arrangement constructs, in effect, a pseudo static random access memory.

REFERENCES:
patent: 4079462 (1978-03-01), Koo
patent: 4412314 (1983-10-01), Proebsting
J. G. Posa, "What to Expect Next: a Special Report", Electronics, May 22, 1980, pp. 119-129.
J. G. Posa, "In Memories, C-MOS Speeds up and Redundancy Catches on", Electronics, Feb. 24, 1981, pp. 141-146.
H. Leung et al., "Storage Cell Restore Circuit", IBM Technical Disclosure Bulletin, vol. 12, No. 12, May 1970, p. 2213.
Elektronic 1976, Heft 10, pp. 59-61.
M. Taniguchi et al., "Fully Boosted 64K Dynamic RAM with Automatic and Self-Refresh", IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981, pp. 492-498.

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