Dynamic memory word line driver scheme

Details Dynamic memory word line driver scheme Dynamic memory word line driver scheme

2000-04-13

2001-08-21

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189060, C365S230060

Reexamination Certificate

active

06278640

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to CMOS dynamic random access memories (DRAMs), and particularly to word line drivers.
BACKGROUND TO THE INVENTION
Dynamic random access memories are generally formed of a matrix of bit lines and word lines with memory cells located adjacent the intersections of the bit lines and word lines. The memory cells are enabled to provide their stored bits to the bit lines or to permit a write operation by signals carried on the word lines.
Each memory cell is typically formed of a bit storage capacitor connected to a reference voltage and through the source-drain circuit of an “access” field effect transistor to an associated bit line. The gate of the field effect transistor is connected to the word line. A logic signal carried by the word line enables the transistor, thus allowing charge to flow through the source-drain circuit of the transistor to the capacitor, or allowing charge stored on the capacitor to pass through the source-drain circuit of the access transistor to the bit line.
In order for the logic level V
dd
potential from the bit line to be stored on the capacitor, the word line must be driven to a voltage above V
dd
+V
tn
, where V
tn
is the threshold voltage of the access transistor including the effects of back bias.
During the early days of DRAM design, NMOS type FETs, that is, N-channel devices were used exclusively. In order to pass a V
dd
+V
tn
level signal to the selected word line, the gate of the pass transistor had to be driven to at least V
dd
+2V
tn
. Furthermore, to allow sufficient drive to achieve a voltage greater than V
dd
+V
tn
on the word line within a reasonable length of time in order to facilitate a relatively fast memory, the gate of the pass transistor is driven to a significantly higher voltage. In such devices, the word line driving signal utilized capacitors in a well-known double-boot strap circuit.
In the above circuit, the boot strapping voltage circuit is designed to exceed the voltage V
dd
+2V
tn
, in order to ensure that temperature, power supply, and process variations would never allow the pass transistor driving voltage to fall below V
dd
+2V
tn
.
However, it has been found that in small geometry VLSI memories, the high voltages provided by the boot-strap circuits can exceed the tolerable voltages in the memory, thus adversely affecting reliability.
SUMMARY OF THE INVENTION
The present invention is a circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained.
According to an embodiment of the invention a dynamic random access memory (DRAM) is comprised of word lines, memory cells having enable inputs connected to the word lines, apparatus for receiving word line selecting signals at first logic levels V
ss
and V
dd
, and for providing a select signal at levels V
ss
and V
dd
, a high voltage supply source V
pp
which is higher in voltage than V
dd
, a circuit for translating the select signals at levels V
ss
and V
dd
to levels V
ss
and V
pp
and for applying it directly to the word lines for application to the enable inputs whereby an above V
dd
voltage level word line is achieved without the use of double boot-strap circuits.
According to another embodiment, a dynamic random access memory (DRAM) is comprised of bit lines and word lines, memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a bit charge storage capacitor, the access field effect transistor having a gate connected to a corresponding word line; a high supply voltage source V
pp
; a circuit for selecting the word line and a circuit having an input driven by the selecting apparatus for applying the V
pp
supply voltage to the word line.


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