Dynamic memory word line driver scheme

Details Dynamic memory word line driver scheme Dynamic memory word line driver scheme

1995-08-16

1998-10-13

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365226, 36523006, G11C 800

Patent

active

058222537

ABSTRACT:
A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM is comprised of bit lines and word lines, memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a high logic level voltage V.sub.dd bit charge storage capacitor, the field effect transistor having a gate connected to a corresponding word line; a high V.sub.pp supply voltage source which is in excess of high logic level voltage V.sub.dd plus one transistor threshold voltage but less than a transistor damaging voltage; means for selecting the word line and means having an input driven by the selecting means for applying the V.sub.pp supply voltage level directly to the word line through the source-drain circuit of an FET. Thus an above V.sub.dd voltage level on the word line is achieved without the use of double boot-strap circuits.

REFERENCES:
patent: 4189782 (1980-02-01), Dingwall
patent: 4730132 (1988-03-01), Watanabe et al.
patent: 4814647 (1989-03-01), Tran
patent: 5031149 (1991-07-01), Matsumoto et al.
patent: 5038327 (1991-08-01), Akaogi
patent: 5150325 (1992-09-01), Yanagisawa et al.
Kitsukawa, Goro et al., "A 1-Mbit BiCMOS DRAM Using Temperature-Compensation Circuit Techniques," IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 597-601.
Kitsukawa, Goro et al., "A 23-ns 1-Mb BiCMOS DRAM," IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1102-1111.
Nakagome, Yoshinobu et al, "An Experimental 1.5-V 64-Mb DRAM," IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 465-472.
Fujii, Syuso et al., "A 45-ns 16-Mbit DRAM with Triple-Well Structure," IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1170-1174.
Gillingham, Peter et al., "High-Speed, High-Reliability Circuit Design for Megabit DRAM," IEEE Journal of Solid-State Circuits, vol. 26, No. 8, Aug. 1991, pp. 1171-1175.

Affiliated with

Also associated with

Rating

Dynamic memory word line driver scheme does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic memory word line driver scheme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic memory word line driver scheme will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-320297