Dynamic memory with increased data retention time

Details Dynamic memory with increased data retention time Dynamic memory with increased data retention time

1985-05-28

1987-07-07

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Data refresh

365205, 365190, G11C 700

Patent

active

046791728

ABSTRACT:
A dynamic memory obtains reduced leakage currents through the access transistors by preventing the low-going column conductors from reaching zero volts for at least a majority of the duration of the active portion of a memory cycle. The low-going conductors are allowed to reach zero volts during the refresh operation. One advantage is a possible increase in the data storage time between required refresh operations. An increase in the refresh interval is especially useful for memory operations wherein a multiplicity of columns are selected for a given row selection. The present technique also addresses the tendency toward increased sub-threshold leakage as field effect transistor thresholds decrease.

REFERENCES:
patent: 4204277 (1980-05-01), Kinoshita
patent: 4447892 (1984-05-01), Zibu
patent: 4475178 (1984-10-01), Kinoshita
patent: 4551641 (1985-11-01), Pelley, III
Gray, "Three Level Word Line Pulse for Single FET Cell Arrays", IBM Technical Disclosure Bulletin, vol. 20, No. 5, pp. 1718-1719, Oct. 1977.

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