Dynamic memory throttling for power and thermal limitations

Details Dynamic memory throttling for power and thermal limitations Dynamic memory throttling for power and thermal limitations

2006-06-20

2006-06-20

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S212000, C713S330000, C713S323000, C713S401000, C700S299000, C702S132000

Reexamination Certificate

active

07064994

ABSTRACT:
In one embodiment, a memory controller is coupled to a memory subsystem and controls accesses to the memory subsystem. In addition, a temperature sensor is positioned to detect a temperature associated with the memory subsystem. In this embodiment, the memory controller is configured to selectively insert one or more idle clock cycles between a first memory access and a second memory access depending upon the sensed temperature. In a further embodiment, a sensor is positioned to detect a power condition associated with the memory subsystem. In this embodiment, the memory controller is configured to selectively insert one or more idle clock cycles between a first memory access and a second memory access depending upon the detected power condition.

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