Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1978-07-20
1980-01-22
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Data refresh
307238, G11C 1300
Patent
active
041853237
ABSTRACT:
A memory subsystem for processing memory requests includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes arrays of memory elements corresponding to a number of storage locations, separate addressing and data output circuits. The system further includes common timing, refresh and control circuits. When the memory request specifies a predetermined type of memory operation, the control circuits generate signals for refreshing a location within the memory unit from which data is not being fetched. The control circuits, upon the completion of the refresh operation, in response to another predetermined memory request, refreshes the corresponding row within the other unit in parallel with fetching data from first unit. Upon completing refresh operations within both units, the control circuits generate a control signal for inhibiting the refresh circuits from performing a mandatory refresh operation, upon a row of memory elements within the memory units in which access to the memory system is inhibited temporarily, enabling memory operations to continue without interruption.
REFERENCES:
patent: 3737879 (1973-06-01), Greene et al.
patent: 3790961 (1974-02-01), Palfi et al.
patent: 4028675 (1977-06-01), Frankenberg
Johnson Robert B.
Nibby, Jr. Chester M.
Driscoll Faith F.
Fears Terrell W.
Honeywell Information Systems Inc.
Prasinos Nicholas
Reiling Ronald T.
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