Dynamic memory supporting simultaneous refresh and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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Details

C711S105000, C711S154000, C711S168000, C365S202000, C365S222000

Reexamination Certificate

active

07043599

ABSTRACT:
Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

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Micron data sheet entitled “Synchronous DRAM, MT48LC4M32B2—1 Meg×32×4 banks,” published Jun. 2002. 52 pages.
Preliminary datasheet entitled, “Direct RDRAM™ 256/288-Mbit (4M×16/18×4i),” by Frederick A Ware. Document DL0106 Version 1.1. Copyright Aug. 2000. 72 pages.
Ware, Frederick A. Rambus Preliminary Information, Direct RDRAM 64/72-Mbit (256K×16/18×16d), Doc. DL0035, Version 1.11. Copyright Jun. 2000, Rambus Inc. 68 pgs.
Ware, Frederick A. Rambus Advance Information, Direct RMC.d1 Data Sheet, Doc. DL0036, Version 1.20. Copyright Jul. 2000, Rambus Inc. 100 pgs.

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