Dynamic memory row/column redundancy scheme

Details Dynamic memory row/column redundancy scheme Dynamic memory row/column redundancy scheme

1991-04-05

1993-09-14

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, G11C 700

Patent

active

052455769

ABSTRACT:
A DRAM row or column decoder having a fused stage for disabling defective rows or columns. A fuse is placed within a stage preceding the final output stage of a multi-stage row or column decoder. Because the fuse is not placed within the output stage, it is not necessary to have one fuse for each individual row or column; a single fuse can disable several decoder outputs, and thus several rows or columns can be disabled at the same time.

REFERENCES:
patent: 4587638 (1986-05-01), Isobe
patent: 4791319 (1988-12-01), Tagami
patent: 4829481 (1989-05-01), Johnson
patent: 4881202 (1989-11-01), Tsujimoto
patent: 4972105 (1990-11-01), Burton
patent: 5103426 (1992-04-01), Hidaka
patent: 5107464 (1992-04-01), Sahara
patent: 5126973 (1992-06-01), Gallia

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