Dynamic memory refresh system with additional refresh cycles

Details Dynamic memory refresh system with additional refresh cycles Dynamic memory refresh system with additional refresh cycles

1980-06-24

1982-05-04

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365189, G11C 1140

Patent

active

043285660

ABSTRACT:
The present invention is particularly directed to the enabling of a refresh cycle for a dynamic memory chip at a period in the fetch cycle, for example, of a type 8085 microprocessor, when the normal timing of the chip does not permit addressing of the memory. Specifically, in the fetch cycle, a fourth clock period occurs following a memory read pulse. This fourth clock cycle is required for the application of the microprocessor, but does not involve any addressing of the memory. Accordingly, in accordance with the invention, upon the occurrence of a memory read cycle, during which a normal refresh occurs, the refreshing circuitry is reactivated, so that a further refresh cycle will occur during this fourth clock.

REFERENCES:
patent: 4028675 (1977-06-01), Frankenberg
patent: 4106108 (1978-08-01), Cislaghi et al.

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