Dynamic memory refresh controller utilizing array voltage

Details Dynamic memory refresh controller utilizing array voltage Dynamic memory refresh controller utilizing array voltage

1996-07-17

1997-11-04

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365149, 365233, 3652257, G11C 700

Patent

active

056847513

ABSTRACT:
Self refresh timing in a low-power dynamic memory system is governed by an oscillator having a voltage dependent resistor and a process dependent capacitor. The resistor increases in resistance to compensate for increased applied power supply voltage and variation in substrate bias voltage. The total capacitance needed for a given oscillator center frequency is made up of a plurality of capacitors having the same physical characteristics as the capacitor used in the dynamic memory cell. Power supply voltage, substrate bias voltage, and the physical characteristics of the cell capacitor affect the cell's data retention time. By compensating the oscillator for these effects, refreshing is optimally accomplished within the data retention time. A system having compensated refresh timing according to the invention is more appropriate for low power applications due to the resulting decreased power consumption.

REFERENCES:
patent: 4771406 (1988-09-01), Oishi et al.
patent: 5400289 (1995-03-01), Blodgett
patent: 5455801 (1995-10-01), Blodgett et al.

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