Dynamic memory refresh circuit

Details Dynamic memory refresh circuit Dynamic memory refresh circuit

1983-11-30

1986-11-25

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365189, G11C 700

Patent

active

046253017

ABSTRACT:
A circuit for generating refresh signals for a dynamic, random access memory is disclosed. The circuit comprises a timer which periodically generates refresh request signals. Each refresh request signal increments a refresh request counter. In normal system operation, after a memory access cycle, a refresh cycle is performed if there is a non-zero count in the counter. At the start of each refresh cycle, the counter is decremented and the refresh address to the memory is changed. Refreshing of the memory continues until the count is zeroed. If, for some reason, memory accesses are not performed within the memory refresh time limit, the count in the counter reaches a critical limit and a non-maskable interrupt is generated to the system processor causing it to access an interrupt vector in the memory and force refresh cycles.

REFERENCES:
patent: 3729722 (1973-04-01), Shuba
patent: 3737879 (1973-06-01), Green et al.
patent: 4106108 (1978-08-01), Cislaghi et al.
patent: 4357686 (1982-11-01), Scheuneman
patent: 4494222 (1985-01-01), White et al.

Affiliated with

Also associated with

Rating

Dynamic memory refresh circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic memory refresh circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic memory refresh circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1161930