Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Patent
1994-11-18
1996-02-27
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
365149, 36518901, G11C 1134
Patent
active
054954436
ABSTRACT:
In a dynamic memory, a ground control circuit is provided for each one memory cell array, and includes a first ground control transistor connected between ground and a source of a grounding transistor in all selection read circuits associated to the corresponding memory cell array. A gate of the transistor is connected to receive a block selection signal which is brought into a selection level at a predetermined timing when the corresponding memory cell array includes a selected memory cell, so that the source of the grounding transistor in all the selection read circuits associated to the corresponding memory cell array are connected to the ground through the first ground control transistor. Two second ground control transistors having a current drive capacity smaller than that of the first ground control transistor, are connected in parallel to the first ground control transistor. A gate of the second ground control transistors is connected to receive a plurality of reset signals which are in common to the plurality of memory cell arrays and which are brought into an active level at different timings during a period excluding an active period of the plurality of sense amplifiers.
REFERENCES:
"A 45-ns 64-Mb DRAM with a Merged Match-Line Test Architecture"; Shigeru Mori et al.; IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991; pp. 1486-1491.
"An Experimental 1.5-V 64-Mb DRAM"; Yoshinobu Nakagome et al.; IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991; pp. 465-471.
Taguchi et al. "A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture" IEEE of Solid-State Citcuits vol. 26, No. 11, Nov. 1991, pp. 1493-1497.
Nakagome et al. "A 1.5 Circuit Technology for 64 Mb DRAMs" 1990 Symposium on VLSI Circuits, Jun. 1991, pp. 17-18.
Nakagome et al. "Reviews and Prospects of DRAM Technology" Transactions of the Institute of Electronics, Information and Communication Engineers of Japan vol. E74, No. 4, Apr. 1991 pp. 799-810.
NEC Corporation
Nelms David C.
Niranjan F.
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