Dynamic memory device with refresh circuit and refresh method

Details Dynamic memory device with refresh circuit and refresh method Dynamic memory device with refresh circuit and refresh method

1997-11-24

1999-02-23

Nelms, David

Static information storage and retrieval

Read/write circuit

Data refresh

36518511, 36518522, 36523003, G11C 700

Patent

active

058751432

ABSTRACT:
A refresh circuit (230) and a method for the refresh of dynamic memory devices (201) are described where the rows to be refreshed are determined by a logical function and by a reference address (223). The availability of refresh signals (215) for the rows at the outputs (217) of a decoder (214) is determined by control logic (224) which is connected to an address generator (212) and to a reference register (222) which contains a reference address (223). By supplying the reference address (223) to the refresh circuit (230) it is possible to determine which rows are to be refreshed. The memory array (210) of the dynamic memory device (201) can be refreshed partially and energy consumption for the refresh can be reduced.

REFERENCES:
patent: 4914630 (1990-04-01), Fujisthima et al.
patent: 5247655 (1993-09-01), Khan et al.

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