Dynamic memory device with circuits for setting self-refreshing

Details Dynamic memory device with circuits for setting self-refreshing Dynamic memory device with circuits for setting self-refreshing

1997-04-15

1999-01-19

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Data refresh

365233, G11C 700

Patent

active

058620931

ABSTRACT:
Control signals for refreshing interval selection is simplified and yield in production of a dynamic memory device is improved by a dynamic memory device of the invention. The dynamic memory device includes a refreshing timing signal generating portion for generating first and second refreshing timing signal having mutually different periods, refreshing timing selection means for detecting a time difference of level variation timing of two or three external control signals and generating a refreshing timing selection signal of selected one of first and second levels depending upon the time difference, selector for selecting one of the first and second refreshing timing signal depending upon the level of the refreshing timing selection signal, self-refreshing detecting means for detecting a time condition of level variation timing of a plurality of external control signals and generating an active level self-refreshing entry signal, and an internal address generating means for generating an internal address signal sequentially updated an address value in synchronism with the refreshing timing signal selected by the selector while the self-refreshing entry signal is in active level.

REFERENCES:
patent: 5471430 (1995-11-01), Sawada et al.
patent: 5495452 (1996-02-01), Cha
patent: 5717652 (1998-02-01), Ooishi

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