Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-10-30
2004-05-18
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230060
Reexamination Certificate
active
06738304
ABSTRACT:
TECHNICAL FIELD
The invention relates to dynamic memories according to the preamble of claim
1
and a method for refreshing the content of such a dynamic memory according to the preamble of claim
6
.
BACKGROUND ART
Hitherto, the rising current consumption of ever larger memories has been covered by correspondingly larger current supplies. In order to counteract the evolution of heat and the energy consumption—particularly in the case of portable devices—special power-down modes, etc. are employed. If the memory is not currently being accessed, unrequired functions are turned off, and the current supply is correspondingly reduced.
Such a semiconductor memory is known e.g. from U.S. Pat. No. 6,172,928, in which, in the course of the refresh operation, a first current supply supplies the elements of the memory in the normal operating mode, but not in the power-reduced operating mode. In the course of the refresh operation, a second current supply supplies the elements of the memory in the power-reduced operating mode, but not in the normal operating mode.
The disadvantage with this prior art is that the circuit becomes more costly and more complex due to the second current supply and its control.
SUMMARY OF THE INVENTION
It is an object of the invention to reduce the power loss of a memory system in operation with a minimal outlay on circuitry.
This object is achieved according to the invention by means of a dynamic memory device according to claim
1
and by means of a method for controlling such a dynamic memory device according to claim
6
. The subclaims relate to preferred embodiments of the invention.
During the operation of a data processing system with dynamic memories, it is generally the case that only a part of at least one dynamic memory is occupied. However, in the prior art, the dynamic memory is always refreshed in its entirety at predetermined time intervals. According to the invention, by contrast, the rows and/or columns of a memory which are not occupied with values are masked out by selective measures during the refresh. The masked-out rows and/or columns are then not refreshed either in the case of autorefresh commands or in the self-refresh mode. In other words, an insertion and masking-out possibility of rows and/or columns of a memory at the operating time of the system is introduced which is determined by the actually occupied memory locations and is thus virtually user-programmable.
Accordingly, the dynamic memory device having at least one memory matrix having a plurality of memory cells arranged in rows and columns, the memory cells in a row being connected by in each case one of a plurality of word lines and the memory cells in a column being connected by in each case one of a plurality of bit lines, at least one sense amplifier for reading data from the memory cells via the plurality of bit lines, at least one row address decoder and at least one column address decoder for generating a memory-internal address in a manner dependent on a memory-external address signal, a sequence control device for cyclically generating refresh addresses for carrying out a refresh operation of the memory cells, is characterized by a selection device for selectively skipping addresses of memory cells which are not occupied, during the cyclic generation of the plurality of refresh addresses.
In particular, in the dynamic memory device, the selection device comprises an address generator for generating a refresh address, an address register, in which unoccupied memory addresses are stored, and a logic circuit, which outputs a masking-out signal when an address generated by the address generator corresponds to an address stored in the address register, so that the address generator directly generates a further refresh address.
Depending on the application and implementation of the invention, row addresses or column addresses can be stored in the address register.
In a dynamic memory device in which the memory cells are distributed between a plurality of memory banks, each memory bank comprising a sense amplifier for reading data from the memory cells via the plurality of bit lines and a row address decoder and a column address decoder for generating a memory-internal address in a manner dependent on a memory-external address signal, the selection device for selectively skipping addresses during the cyclic generation of the plurality of refresh addresses of memory cells in the respective memory bank which are not occupied is distributed between the plurality of memory banks.
The method according to the invention for refreshing a memory content of such a dynamic memory device is characterized by selective skipping of addresses of memory cells which are not occupied, during the cyclic generation of the plurality of refresh addresses, by a selection device.
Generally, in the case of the method, the refresh operations of the memory cells can be carried out in a burst mode, a cycle stealing mode or in a hidden refresh mode.
One advantage of the invention is that the availability of the memory is increased through the reduction of the cells to be refreshed and thus of the total refresh duration.
Further features and advantages of the invention emerge from the following description of preferred embodiments, in which reference is made to the accompanying drawings.
REFERENCES:
patent: 5239505 (1993-08-01), Fazio et al.
patent: 5535169 (1996-07-01), Endo et al.
patent: 5644544 (1997-07-01), Mizukami
patent: 6167484 (2000-12-01), Boyer et al.
patent: 101 43 766 (2003-04-01), None
Ohsawa et al., “Optimizing the DRAM Refresh Count for Merged DRAM/Logic LSIs,” p. 82-87, (1998).
Kim et al., “Block-Based Multi-Period Refresh for Energy Efficient Dynamic Memory,” IEEE (USA), p. 193-197, (2001).
Takase et al., “A 1.6-GByte/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme,” IEEE Journal of Solid-State Circuits (USA), vol. 34 (No. 11), (1999).
Christoph et al., “Schnellerer Zugriff zum Arbeitsspeicher,” Elektronik, p. 65-67, (1984).
Benedix Alexander
Dankowski Stefan
Dueregger Reinhard
Ruf Wolfgang
Jenkins & Wilson & Taylor, P.A.
Tran M.
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