Dynamic memory clock control system and method

Details Dynamic memory clock control system and method Dynamic memory clock control system and method

1998-08-07

2002-10-01

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S150000, C711S151000, C711S158000, C711S167000, C713S501000, C713S322000, C713S323000, C713S502000, C365S227000

Reexamination Certificate

active

06460125

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates generally to circuits and methods for reducing power consumption for electronic circuits, and more particularly to circuits and methods that control a memory clock and/or memory controller to reduce power consumption.
Portable electronic devices such as notebook computers, personal organizers, portable telecommunication equipment and other electronic devices consume much power during their display mode. By way of example, graphics control chips for laptop computers may be integrated circuits having dynamic ram (DRAM) on the same die as the memory controller and other video and graphics processors. As shown in
FIG. 1
for example, a conventional type of graphics control chip
100
may include a number of memory access request circuits (or access request engines) such as a video capture engine
102
, a two dimensional and three dimensional drawing engine
104
, a display engine
106
, a video playback engine
108
, a host processor
109
, onboard DRAM
110
serving as the memory, a memory controller
112
and a phase lock loop circuit (PLL)
114
for generating a memory clock. As known in the art, each engine
102
-
108
may have another clock, other than the memory clock, creating a clock boundary
116
. Graphics control chips typically also include another phase lock loop circuit
118
for generating a clock for a display device (or devices) such as a CRT
120
a
that may plug into the laptop computer or an LCD display
120
b
that is mounted to the laptop computer. A central processing unit (CPU) of the computer
122
interfaces with the graphics chip and other peripheral devices as known in the art. A laptop computer or a portable device may include a TV tuner
124
, as part of a multimedia package, that sends video information
126
to the video capture engine
102
for eventual display on LCD display
120
b
after being stored in the memory
110
.
With chips such as graphics controller chips, the many graphic engines
102
-
108
attempt to access the memory
110
to perform their necessary operations. However only one of the graphic engines can access the memory
110
at a given time. Some of the display operations require real-time processing, such as video capture operation, display operation and video playback, so that real-time display can occur on the LCD display
120
b.
For example, where the TV tuner is applying video to the video capture engine
102
, the video should be processed in real-time to facilitate display in real-time which is necessary, for example, for live performances or when the TV tuner is providing live feed. Hence this engine has a higher priority over, for example, a 2D or 3D drawing engine
104
which may be slightly delayed and still provide the user with high performance on display times. In conventional systems, that employ video capture engines for example, the memory clock frequency is set at the highest possible frequency to ensure suitable graphic controller performance. However, this results in a higher power dissipation which can degrade the overall system performance of a portable electronic device and fail to conserve battery power. If the memory clock is set to a lower speed, the real-time operations may not process information fast enough and suffer unnecessarily at the expense of reduced power consumption.
A problem arises with such devices since power consumption and thermal dissipation need to minimized for portable devices without unnecessarily sacrificing operational performance. The power dissipation of a graphics control chip and other integrated circuits is typically related to the frequency of the memory clock. Systems such as those shown in
FIG. 1
typically have a fixed memory clock
128
which can be manually changed by the user through a graphical user interface but is typically factory set upon initialization and often does not change.
Consequently, there exists a need for a dynamic power reduction circuit that can reduce power consumption and power dissipation without unnecessarily degrading system performance. It would be advantageous, if such a system could detect memory access demand and automatically adjust memory clock frequency accordingly to facilitate power reduction and increase display capabilities during proper times.


REFERENCES:
patent: 5781768 (1998-07-01), Jones, Jr.
patent: 5804749 (1998-09-01), Shirakawa et al.
patent: 6073223 (2000-06-01), McAllister et al.
patent: 6079025 (2000-06-01), Fung
patent: 6112310 (2000-08-01), Jun et al.

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