Dynamic memory circuit with automatic refresh function

Details Dynamic memory circuit with automatic refresh function Dynamic memory circuit with automatic refresh function

2000-10-17

2002-08-20

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

Reexamination Certificate

active

06438055

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory circuit which requires a refresh operation for maintaining stored data, such as a dynamic RAM (DRAM), and more particularly to a dynamic memory circuit which automatically performs a refresh without requiring a refresh instruction from outside.
2. Description of the Related Art
A DRAM, which is widely used as a large capacity memory device, uses a volatile memory cell which consists of one transistor and one capacitor, so a periodic refresh is necessary to maintain stored data.
Generally speaking, refresh is classified into auto refresh, which is performed by responding to an external command in normal mode, and self refresh, which the memory device automatically performs in power down mode.
Before describing refresh, a configuration of a conventional synchronous type dynamic memory circuit will be described.
FIG. 24
shows a configuration of a conventional synchronous type dynamic memory circuit. The memory circuit shown in
FIG. 24
comprises two memory banks BANK
0
and BANK
1
, which are the memory core. The peripheral circuits shared by these memory banks are, a clock input buffer
10
which inputs a clock CLK from outside according to the state of a clock enable signal CKE and supplies an internal clock CLK
1
to internal blocks, a command decoder
12
which latches a command input CMD from outside and decodes it, an address buffer
14
which latches an address from outside, a data input/output buffer register
16
which outputs or inputs data to the data input/output terminal DQ, a self refresh control part
18
which generates an internal self refresh signal S-REF
1
responding to a self refresh command S-REF, and a refresh address counter
22
.
In each memory bank, a plurality of blocks BLK which have a memory cell array MC, a row decoder RDEC and a sense amplifier SA and a column decoder CDEC respectively, a command latch
24
shared by the blocks BLK, a control circuit
26
which supplies control signals corresponding to the block responding to various commands RD, WR and REF from the command latch
24
, and a selector
28
which selects either a refresh address from the refresh address counter
22
or an external address from the address buffer
14
, are disposed. The blocks BLK are connected to the input/output data bus I/ODB, which is shared by the banks, via the data bus DB, and the sense buffer/write amplifier SB/WA.
Auto refresh is performed in normal mode where data is read or written, responding to an external command. In this case, refresh refers to a procedure to select a memory cell MC, amplify the information by the sense amplifier SA, and rewrite it back to the memory cell. Therefore a write or read operation cannot be instructed to the memory cell block during refresh. So in normal mode, a refresh operation is executed responding to an auto refresh command from outside, so that the refresh operation does not collide with a read or write operation. An address to select a memory cell to be refreshed, however, is automatically generated inside the memory device. This is “auto refresh”.
Specifically, in a prior art in
FIG. 24
, a refresh signal REF is latched by the command latch
24
when the auto refresh command A-REF is input from outside, and the control circuit
26
controls the refresh operation based on the refresh signal REF. The refresh address is automatically generated by the refresh address counter
22
, and the selector
28
selects and supplies a refresh address to the memory block BLK responding to a select signal SEL supplied by the control circuit
26
during refresh. The refresh address counter
22
is counted up eachtime refresh is performed.
Self refresh, on the other hand, is. a refresh automatically performed by the device in power down mode. In power down mode, the memory device deactivates input buffers
10
,
12
and
14
, so as to stop receiving input signals from outside, and also stops supplying the clock CLK
1
to the inside. In this state,a periodic refresh is necessary. So the self refresh control part
18
starts the operation when the device enters power down mode by a clock enable signal CKE to instruct power down. The self refresh control part
18
generates a self refresh instruction signal S-REF
1
responding to a timing signal which the oscillator
20
, mounted on the device, generates at a predetermined cycle, and the control circuit
26
controls the refresh operation based on the signal S-REF
1
. The operation of the refresh address counter
22
and the selector
28
is the same as auto refresh.
When such a memory device (DRAM) is mounted in a computer system, refresh has a problem. Especially when auto refresh is performed in normal operation mode, the controller device controlling the memory device must manage the refresh timing of the memory device and supply a refresh command periodically. This control becomes a burden for the controller device.
Also, the memory controller cannot issue a read or write command during the period of auto refresh, which interferes with increasing the speed of the system. To solve this problem, it is discussed in Japanese Patent Laid-Open No. 61-71494 that one write or read operation cycle is divided into two time zones, wherein a write or read operation is performed during one of the time zones, and a refresh operation is performed during the other time zone. However, the semiconductor storage device of this patent has a relatively slow operation speed, and this invention cannot be simply applied to current synchronous type memory devices.
In the case of a synchronous type memory device (SDRAM), where the command cycles are controlled synchronizing with the clocks to be supplied, the activation of the memory core and a read or write operation are all controlled by commands to be supplied, synchronizing with the clocks. Also the operation cycle is fast. Therefore during a normal operation mode period, a voluntary refresh operation by the memory device is inhibited so that a read or write command to be supplied at an arbitrary timing can be handled, as mentioned above. As a result, the outside memory controller controls refresh during the normal operation mode period, and supplies an auto refresh command at a predetermined timing.
Also, in the case of a synchronous type memory device, a read operation and a write operation are not always controlled at the same timing. So it is difficult to execute a read or write operation during one of the two time zones and execute a refresh operation during the other time zone, as in the above mentioned prior art.
SUMMARY OF THE INVENTION
With the foregoing in view, it is an object of the present invention to provide a dynamic memory circuit which does not require refresh control by the memory controller.
It is another object of the present invention to provide a dynamic memory circuit which can automatically perform a refresh operation even in normal operation mode.
It is still another object of the present invention to provide a dynamic memory circuit where increasing the speed of the system is not interfered by a refresh operation.
It is still another object of the present invention to provide a dynamic memory circuit which has a new internal operation cycle and can automatically perform a refresh operation internally.
To achieve the above objects, a first aspect of the present invention is that in a dynamic memory circuit, first and second internal operation cycles are assigned to one external operation cycle according to external commands, a memory core performs a read operation which corresponds to a read command at the first internal operation, and performs a refresh operation which responds to a refresh command at the second internal operation cycle. Also the memory core performs a refresh operation which responds to a refresh command at the first internal operation cycle, and performs a write operation which corresponds to a write command at the second internal operation cycle. It is preferable that when the read or write command is not input

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